Memory

• US 7,933,148 B2
• Filed: 09/18/2009
• Issued: 04/26/2011
• Est. Priority Date: 02/15/2005
• Status: Active Grant

• Current Assignee: OL Security LLC (Intellectual Ventures LLC)
• Original Assignee: Patrenella Capital Ltd LLC (Intellectual Ventures LLC)
• Inventors: Yamada, Kouichi, Murayama, Yoshiki
• Primary Examiner(s): Le; Vu A
• Assistant Examiner(s): Yang; Han
• Application Number:
  US12/562,724
• Publication Number:
  US 20100008164A1
• Time in Patent Office: 585 Days
• Field of Search: 365/177, 365/149, 365/196
• US Class Current: 365/177
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods

Abstract

A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor.

Claims

1. An apparatus, comprising:

a memory cell coupled to a bit line and configured to hold data, wherein the data includes first data or second data;

a first transistor having at least a base, wherein the first transistor is configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read; and

a second transistor having at least a first terminal, a second terminal, a third terminal, and a channel between the second and third terminals, wherein the second transistor is configured to feed different quantities of currents to the base of the first transistor through the channel, in response to reading the first data or the second data, by changing a potential difference between a first terminal of the second transistor and either a second terminal or a third terminal of the second transistor;

wherein the first transistor has a collector coupled to a first end of a third transistor, and wherein a second end of the third transistor is coupled to a sense amplifier.

2. The apparatus of claim 1, wherein the first transistor comprises a bipolar transistor, and wherein the second transistor comprises a field-effect transistor.

3. The apparatus of claim 1, wherein the memory cell comprises a ferroelectric memory cell.

4. The apparatus of claim 1, wherein the memory cell comprises a phase-change memory cell.

5. The apparatus of claim 1, wherein the memory cell comprises a resistance-change memory cell.

6. An apparatus, comprising:

a memory cell coupled to a bit line and configured to hold data; and

a first transistor having a control terminal selectively coupleable to the bit line, wherein the first transistor is configured to read the data by amplifying a current corresponding to the data that appears on the bit line if the data is read;

wherein a second terminal of the first transistor is coupled to a first end of a second transistor, and wherein a second end of the second transistor is coupled to a sense amplifier.

7. The apparatus of claim 6, further comprising a resistor having a resistance larger than an interconnection resistance and having a first end coupled to the second terminal of the first transistor, wherein a second end of the resistor is configured to receive a positive potential while a negative potential is applied to a third terminal of the first transistor.

8. The apparatus of claim 6, wherein the first transistor comprises a bipolar transistor, and wherein the second transistor comprises a field-effect transistor.

9. The apparatus of claim 6, wherein the memory cell comprises a ferroelectric memory cell.

10. The apparatus of claim 6, wherein the memory cell comprises a phase-change memory cell.

11. The apparatus of claim 6, wherein the memory cell comprises a resistance-change memory cell.

21. The apparatus of claim 6, wherein the control terminal of the first transistor is selectively coupleable to the bit line through a third transistor.

12. An apparatus, comprising:

a memory cell coupled to a bit line and configured to hold data, wherein the data includes first data or second data; and

an amplification circuit comprising a bipolar transistor having a base coupled to the bit line and configured to receive an input current corresponding to the data that appears on the bit line if the data held in the memory cell is read, wherein the amplification circuit is further configured to apply the input current and to generate an output current having a first magnitude if the first data is read or a second magnitude if the second data is read.

13. The apparatus of claim 12, wherein a second terminal of the bipolar transistor is configured to provide the output current.

14. The apparatus of claim 13, wherein the second terminal of the bipolar transistor comprises a collector.

15. The apparatus of claim 13, wherein a difference between the first and second magnitudes is greater than a difference between currents appearing on the bit line if reading the first data or the second data.

16. The apparatus of claim 13, wherein the memory cell comprises a ferroelectric memory cell.

17. The apparatus of claim 13, wherein the memory cell comprises a phase-change memory cell.

18. The apparatus of claim 13, wherein the memory cell comprises a resistance-change memory cell.

19. The apparatus of claim 13, wherein the memory cell comprises a memory cell of a random access memory (RAM).

20. The apparatus of claim 12, wherein the base of the bipolar transistor is coupled to the bit line through a field-effect transistor.