System and method for high speed communications using digital signal processing

• US 7,933,341 B2
• Filed: 02/28/2001
• Issued: 04/26/2011
• Est. Priority Date: 02/28/2000
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ungerboeck, Gottfried, Parhi, Keshab K., Wakayama, Myles H., Lutkemeyer, Christian A., Vorenkamp, Pieter, Agazzi, Oscar E., Chan, Kevin T.
• Primary Examiner(s): Pascal; Leslie
• Application Number:
  US09/797,428
• Publication Number:
  US 20010035994A1
• Time in Patent Office: 3,709 Days
• Field of Search: 398/202, 398/135, 398/139, 398/140, 398/141, 398/164, 375/229, 375/260, 375/265, 375/296, 375/358, 375/233, 341/141
• US Class Current: 375/260
• CPC Class Codes: G09G 2370/18 Use of optical transmission of display information
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H03M 1/0604 at one point, i.e. by adjusting a single reference value, e.g. bias or gain error gain setting for range control H03M1/18
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 25/4975 Correlative coding using Tomlinson precoding, Harashima precoding, Trellis precoding or GPRS

Abstract

Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation preceding is performed on signals transmitted over an optical channel. In one implementation preceding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Claims

1. A receiver comprising:

a plurality of parallel analog-to-digital converters operable to convert an analog signal into a plurality of digital data streams;

a plurality of parallel forward equalizers, each coupled to an output of one of the analog-to-digital converters to receive a digital data stream; and

a plurality of parallel trellis decoders, each coupled to an output of one of the forward equalizers and operable to produce a decoded data stream, wherein the plurality of parallel trellis decoders are interleaved with respect to each other, wherein the plurality of trellis decoders comprises m trellis decoders operable to receive a block of n samples, and wherein a first of the plurality of trellis decoders processes the first n/m samples, a second of the plurality of trellis decoders processes the second n/m samples, and the mth trellis decoder processes the last n/m samples of the block of samples, wherein m and n are positive integers.

2. The receiver of claim 1 wherein each of the forward equalizers are operable to provide phase equalization of the received digital data stream to produce an equalized digital data stream.

3. The receiver of claim 1 wherein the plurality of parallel analog-to-digital converters are interleaved with respect to each other.

4. The receiver of claim 3 wherein each analog-to-digital converter is driven by a unique phase of a clock signal, so that each analog-to-digital converter samples a different symbol in the received analog signal.

5. The receiver of claim 1 further comprising an optical interface operable to receive an optical communication signal, convert the optical communication signal to an analog electrical signal, and provide the analog electrical signal to the plurality of parallel analog-to-digital converters.

6. The receiver of claim 1 wherein the plurality of parallel trellis decoders comprises a plurality of Viterbi decoders.