Hybrid DC-offset reduction method and system for direct conversion receiver
First Claim
Patent Images
1. An RF receiver circuit for reducing static and dynamic offsets, comprising:
- a low noise amplifier (LNA);
a plurality of down conversion mixers;
a plurality of static compensators coupled to the down conversion mixers;
a plurality of constant gain stages coupled to the static compensators;
a plurality of channel-select low-pass filters connected to the constant gain stages;
a plurality of servo-loop feedback amplifiers connected to the channel-select low pass filters, wherein each of the servo-loop feedback amplifiers comprises a plurality of subtractors, a plurality of variable gain amplifiers, and a plurality of low pass filters, wherein one of the low pass filters is coupled between an output of one of the variable gain amplifiers and a minuend end of one and the plurality of servo-loop feedback amplifiers includes three amplifiers connected in a three-stage configuration, the first amplifier having a maximum gain of Gmax,1, the second amplifier having a maximum gain of Gmax,2, and the third amplifier having a maximum gain of Gmax,3, and wherein a gain mapping block allocates gain G1 to the first amplifier, gain G2 to the second amplifier, and gain G3 to the third amplifier such that a total target gain for the three-stage amplifier G is distributed according to the following conditions;
if G<
=Gmax,1, then setting G1=G, G2=0, and G3=0;
if G>
Gmax,1 and G<
=(Gmax,1 Gmax,2), then setting G1=Gmax,1 and G2=G−
Gmax,1, and G3=0; and
if G>
(Gmax,1+Gmax,2) and G=(Gmax,1+Gmax,2+Gmax,3), then setting G1=Gmax,1, G2=Gmax,2, G3=G−
(Gmax,1+Gmax,2)wherein the gain mapping block is driving the servo-loop feedback amplifiers, and the gain mapping block assigns the gain for each stage in the servo-loop feedback amplifiers in such a way as to use a maximum gain of an earlier stage before assigning an unsatisfied gain to the remaining stages;
a plurality of analog to digital converters; and
an automatic gain feedback control block driving the LNA and the gain mapping block.
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Abstract
A hybrid structure circuit for the cancellation of both Type-I and Type-II DC offsets. It comprises a static compensator in conjunction with a servo-loop feedback amplifier to suppress the undesired DC components present along the path of the base band after the direct conversion mixer. Two mixers are used to down convert a received RF signal directly to a base band signal with two components: in-phase and quadrature-phase. Both in-phase and quadrature-phase branches employ the same circuitry for DC offset cancellation. Miller effect is also utilized in the structure in order to implement the circuit on-chip.
34 Citations
13 Claims
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1. An RF receiver circuit for reducing static and dynamic offsets, comprising:
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a low noise amplifier (LNA); a plurality of down conversion mixers; a plurality of static compensators coupled to the down conversion mixers; a plurality of constant gain stages coupled to the static compensators; a plurality of channel-select low-pass filters connected to the constant gain stages; a plurality of servo-loop feedback amplifiers connected to the channel-select low pass filters, wherein each of the servo-loop feedback amplifiers comprises a plurality of subtractors, a plurality of variable gain amplifiers, and a plurality of low pass filters, wherein one of the low pass filters is coupled between an output of one of the variable gain amplifiers and a minuend end of one and the plurality of servo-loop feedback amplifiers includes three amplifiers connected in a three-stage configuration, the first amplifier having a maximum gain of Gmax,1, the second amplifier having a maximum gain of Gmax,2, and the third amplifier having a maximum gain of Gmax,3, and wherein a gain mapping block allocates gain G1 to the first amplifier, gain G2 to the second amplifier, and gain G3 to the third amplifier such that a total target gain for the three-stage amplifier G is distributed according to the following conditions; if G<
=Gmax,1, then setting G1=G, G2=0, and G3=0;if G>
Gmax,1 and G<
=(Gmax,1 Gmax,2), then setting G1=Gmax,1 and G2=G−
Gmax,1, and G3=0; andif G>
(Gmax,1+Gmax,2) and G=(Gmax,1+Gmax,2+Gmax,3), then setting G1=Gmax,1, G2=Gmax,2, G3=G−
(Gmax,1+Gmax,2)wherein the gain mapping block is driving the servo-loop feedback amplifiers, and the gain mapping block assigns the gain for each stage in the servo-loop feedback amplifiers in such a way as to use a maximum gain of an earlier stage before assigning an unsatisfied gain to the remaining stages; a plurality of analog to digital converters; and an automatic gain feedback control block driving the LNA and the gain mapping block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for amplifier gain allocation to reduce DC offset in an N-stage servo-feedback variable gain amplifier by using a gain mapping block, wherein a target total gain for the N-stage amplifier is G, a maximum gain in each stage is Gmax,1, Gmax,2, . . . , Gmax,N respectively, and a gain setting to each stage is G1, G2, . . . , GN, respectively, the method comprising the following steps:
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if G<
=Gmax,1 then the gain mapping block sets G1=G and Gi=0 for i=2, . . . , N;if G>
Gmax,1 and G<
=(Gmax,1+Gmax,2), then the gain mapping block sets G1=Gmax,1 and G2=G−
Gmax,1, and Gi=0 for i=3 . . . N;if G>
(Gmax,1+Gmax,2) and G=(Gmax,1+Gmax,2+Gmax,3), then the gain mapping block sets G1=Gmax,1, G2=Gmax,2, G3=G−
(Gmax,1+Gmax,2), and Gi=0 for i=4, . . . , N; andthe gain mapping block continues assigning a maximum remaining gain to the first available stage until a desired target total gain G is satisfied. - View Dependent Claims (11)
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12. A method for DC offset reduction for an RF receiver including a low-noise amplifier (LNA), an automatic gain control (AGC) circuit, servo-loops for dynamic DC offset reduction, and a static DC offset reduction circuit, the method comprising:
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resetting the AGC; disabling the servo-loops; setting initial gains for variable gain amplifiers in the servo-loops and the LNA; enabling the servo-loops; releasing the AGC; setting a delay time to allow the servo-loops to settle their gain settings; adjusting gains of LNA; and freezing the AGC; wherein the variable gain amplifiers includes three amplifiers connected in a three-stage configuration, the first amplifier having a maximum gain of Gmax,1, the second amplifier having a maximum gain of Gmax,2, and the third amplifier having a maximum gain of Gmax,3, and wherein gain G1 is allocated to the first amplifier, gain G2 is allocated to the second amplifier, and gain G3 is allocated to the third amplifier such that a total target gain for the three-stage amplifier G is distributed according to the following conditions; if G<
=Gmax,1, then setting G1=G, G2=0, and G3=0;if G>
Gmax,1 and G<
=(Gmax,1+Gmax,2), then setting G1=Gmax,1 and G2=G−
Gmax,1, and G3=0; andif G>
(Gmax,1+Gmax,2) and G<
=(Gmax,1+Gmax,2+Gmax,3), then setting G1=Gmax,1, G2=Gmax,2, G3=G−
(Gmax,1+Gmax,2). - View Dependent Claims (13)
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Specification