Data access and permute unit

• US 7,933,405 B2
• Filed: 04/08/2005
• Issued: 04/26/2011
• Est. Priority Date: 04/08/2005
• Status: Active Grant

• Current Assignee: Icera Inc. (NVIDIA Corporation)
• Original Assignee: Icera Inc. (NVIDIA Corporation)
• Inventors: Knowles, Simon, Felix, Stephen
• Primary Examiner(s): CERVETTI, DAVID GARCIA
• Application Number:
  US11/102,266
• Publication Number:
  US 20060227966A1
• Time in Patent Office: 2,209 Days
• Field of Search: 380/42, 380/37, 380/47
• US Class Current: 380/42
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction

Abstract

According to embodiments of the invention, there is disclosed a data processing unit, a method of operating the same, computer program product and an instruction. In one embodiment according to the invention, there is provided a data processing unit for a computer processor, the data processing unit comprising a deep register access mechanism capable of performing a permutation operation on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) register access for the data operand and (ii) execution of a data processing operation on the operand.

Claims

1. A data processing unit for a computer comprising:

a register file;

a register access and permute unit capable of accessing at least one data operand in said register file based on a single data access instruction, said register access and permute unit comprising permute circuitry operable to selectively permute said accessed data operand based on a permute opcode portion of said single data access instruction; and

a data execution unit arranged in series with said register access and permute unit, said data execution unit being operable to perform an operation on said selectively permuted data operand based on an execution opcode portion of said single data access instruction.

2. A data processing unit as in claim 1, wherein said register access and permute unit comprises a decoder register file read stage connected between said register file and said execution unit.

3. A data processing unit as in claim 2, wherein said register access and permute unit comprises at least one multiplexer stage connected between said decoder register file read stage and said execution unit.

4. A data processing unit as in claim 3, wherein a permute control input is supplied to said multiplexer stage.

5. A data processing unit as in claim 2, wherein said register access and permute unit further comprises a column multiplexer stage connected between said decoder register file read stage and said execution unit.

6. A data processing unit as in claim 5, wherein a permute control input is supplied to said column multiplexer stage.

7. A data processing unit as in claim 2, wherein said register access and permute unit comprises a crossbar multiplexer stage connected between said decoder register file read stage and said execution unit.

8. A data processing unit as in claim 7, wherein a permute control input is supplied to said crossbar multiplexer stage.

9. A data processing unit as in claim 2, wherein a permute control input is supplied to said decoder register file read stage.

10. A data processing unit as in claim 1, comprising bypass circuitry connected between an output of said execution unit and an input of said register file access and permute unit.

11. A data processing unit as in claim 1, comprising first and second register access and permute circuitry.

12. A data processing unit as in claim 11, wherein said first register access and permute circuitry is arranged to access first and second operands and to perform a permutation selected from one or more of a roll, a sort, a shuffle.

13. A data processing unit as in claim 11, wherein said second register access and permute circuitry is arranged to access at least one operand and to perform a broadcast permutation.

14. A data processing unit as in claim 11, wherein said first and second register access and permute circuits each comprises one or more of:

(i) a decoder register file read stage connected between said register file and said execution unit;

(ii) at least one multiplexer stage connected between said decoder register file read stage and said execution unit.

15. A data processing unit as in claim 14, wherein said at least one multiplexer stage comprises one or more of:

(i) a column multiplexer stage connected between said decoder register file read stage and an execution unit; and

(ii) a crossbar multiplexer stage connected between said column multiplexer stage and said execution unit.

16. A data processing unit as in claim 1, wherein said execution unit comprises single-instruction, multiple-data circuitry.

17. A data processing unit for a computer processor comprising, in series connectivity, a register access unit, vector permutation circuitry, and at least one execution unit, the apparatus further comprising a decode unit operable, responsive to a single instruction, to control access to at least one vector operand, to selectively permute the at least one vector operand, and to execute at least one further operation.

18. A method of operating a data processing unit for a computer processor, the method comprising:

performing, by said data processing unit of said computer processor, a permutation operation responsive to a single data access instruction on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) accessing a register to obtain said at least one data operand and (ii) executing a data processing operation on said at least one data operand; and

performing, by said data processing unit of said computer processor, the permutation operation in series with accessing the register based on the single data access instruction.

19. A method according to claim 18, wherein a permutation operation is performed on a single vector register operand.

20. A method according to claim 18, wherein a permutation operation is performed on a plurality of vector register operands.

21. A method according to claim 18, further comprising:

performing multiple consecutive data processing operations on a data operand of a single instruction.

22. A method according to claim 18, wherein performing the permutation operation precedes executing the data processing operation.

23. A method according to claim 18, wherein performing the permutation operation follows executing the data processing operation.

24. A method according to claim 18, wherein a first permutation operation precedes execution of the data processing operation and a second permutation operation follows execution of the data processing operation.

25. A method according to claim 18, further comprising:

selecting the type of the permutation operation from a plurality of permutation operation types based on an opcode portion of said instruction.

26. A method according to claim 18, further comprising selecting the executed data processing operation from:

an arithmetic operation;

a logic operation;

a subsequent permutation operation; and

a processor memory read or write operation.

27. A method according to claim 18, further comprising using a set of permute control inputs to at least partly determine the type of the permutation operation selected from a plurality of permutation operation types.

28. A method according to claim 27, wherein a plurality of permutation operation types available comprises one or more selected from:

a roll permutation, a sort permutation, a shuffle permutation, a broadcast permutation, a select permutation, and another type of permutation operation.

29. A method according to claim 18, further comprising determining the value of a set of permute control inputs based on an opcode portion of the data processing instruction.

30. A method according to claim 18, wherein the data processing unit performs single instruction multiple data execution.

31. A method according to claim 18, wherein performing of the permutation and data processing operation comprises performing at least a portion of an algorithm from the group consisting of:

a Fast Fourier Transform;

Viterbi coding;

Turbo-coding;

a finite impulse response filter algorithm;

another communications algorithm.

32. A method according to claim 18, wherein a first type of permutation operation is performed on a first source operand pair, and a second type of permutation operation is performed on a second source operand.

33. A method according to claim 32, wherein performing the first type of permutation operation comprises performing a permutation from the group consisting of:

a roll permutation and a sort permutation.

34. A method according to claim 32, wherein performing the second type of permutation operation comprises performing a broadcast permutation.

35. A method according to claim 32, wherein performing one or more of the first and second types of permutation operations comprises using 64-bit data-register source arguments.

36. A method according to claim 35, wherein performing the first type of permutation operation allows performing roll operations for forming a single 64-bit result from two 64-bit source values, the 64-bit result corresponding to the source values rolled by an integer number of 16-bit elements.

37. A method according to claim 35, wherein performing the first type of permutation operation allows performing sort operations for forming a single 64-bit result from two 64-bit values, the 64-bit result being selectable as the most significant or the least significant 64-bit sort result.

38. A method according to claim 35, wherein performing the first type of permutation operation comprises performing shuffle operations for interleaving two vectors each consisting of an integer number of 16-bit elements.

39. A method according to claim 35, wherein the integer number of 16-bit elements is an integer power of two.

40. A method according to claim 35, wherein performing the second type of permutation operation allows performing a broadcast operation capable of repeating a 16-bit half-word across a plurality of 16-bit lanes in a 64-bit result.

41. A data processing unit for a computer comprising:

a register file;

a register access and permute unit capable of accessing at least one data operand in said register file based on a single data access instruction, said register access and permute unit comprising first and second register access and permute circuitry operable to selectively permute said accessed at least one data operand based on a permute opcode portion of said single data access instruction, said first register access and permute circuitry arranged to access first and second operands and perform a permutation selected from one or more of a roll, a sort, a shuffle and said second register access and permute circuitry arranged to access at least one operand and to perform a broadcast permutation; and

a data execution unit arranged in series with said register access and permute unit, said data execution unit being operable to perform an operation on said selectively permuted data operand or operands based on an execution opcode portion of said single data access instruction.

42. A method of operating a data processing unit for a computer processor, the method comprising:

performing, by said data processing unit of said computer processor, a permutation operation responsive to a single data access instruction on at least one data operand accessed from a register file of the computer processor, the permutation operation being performed in series with (i) accessing a register to obtain said at least one data operand and (ii) executing a data processing operation on said at least one data operand; and

performing, by said data processing unit of said computer processor, the permutation operation in series with accessing the register based on the single data access instruction, wherein a first type of permutation operation is performed on a first source operand pair, and a second type of permutation operation is performed on a second source operand.