GPS RF front end IC with frequency plan for improved integrability

• US 7,933,627 B2
• Filed: 03/06/2006
• Issued: 04/26/2011
• Est. Priority Date: 12/01/2000
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Tso, Robert
• Primary Examiner(s): SAMS, MATTHEW C
• Application Number:
  US11/370,207
• Publication Number:
  US 20060211399A1
• Time in Patent Office: 1,877 Days
• Field of Search: 455/13.2, 4554561-4566, 455/333, 455/118, 455/260, 455/76, 455/427, 455/552.1, 342/357.1, 342/357.12, 34235701-35717, 342/103, 375/130, 375/316, 375/324, 375/327
• US Class Current: 455/552.1
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence

Abstract

A GPS RF Front End IC using a single conversion stage, which is immune from self jamming from clock signal harmonics generated internally or from dominant clock signal harmonics generated externally by the subsequent baseband GPS processor which uses a clock of 48●fo for GPS processing. The improved frequency plan reduces the problems of interference when the integration of the RF and Baseband functions is required in the form of a single-chip, or as 2 individual chips on a common substrate.

Claims

1. A GPS RF front end integrated circuit comprising:

an RF input for receiving a GPS RF signal;

a mixer in a path of the RF signal for receiving the GPS RF signal and a local oscillator (LO) signal for downconverting the GPS RF signal to an intermediate frequency (IF) signal;

an IF filter in the path of the GPS RF signal for receiving the IF signal, wherein the IF filter is a bandpass filter with a predefined center frequency;

a frequency synthesizer for generating the LO signal; and

a divider circuit to synthesize a GPS processing clock signal from the LO signal, wherein a frequency of the LO signal is an n^th harmonic of the GPS processing clock signal, and a frequency of the GPS processing clock signal is at least twelve times higher than the predefined center frequency of the IF filter,

wherein leakage of the n^th harmonic of the GPS processing clock signal into the path of the GPS RF signal is downconverted and rejected by the IF filter, and wherein a data acquisition clock signal for sampling the received GPS RF signal is obtained by frequency-dividing the GPS processing clock signal.

2. The GPS RF front end integrated circuit of claim 1, where n=32.

3. The GPS RF front end integrated circuit of claim 1, wherein the frequency synthesizer comprises a fractional-N-synthesizer.

4. The GPS RF front end integrated circuit of claim 1, wherein a frequency of the data acquisition clock signal is an integral fraction of a frequency of the GPS processing clock signal.

5. The GPS RF front end integrated circuit of claim 1, wherein a frequency of the data acquisition clock signal is one-third of a frequency of the GPS processing clock signal.

6. A mobile phone comprising:

a GPS receiver having a GPS baseband processor and a GPS RF front end integrated circuit, where the GPS RF front end integrated circuit comprises a frequency synthesizer and a divider circuit, wherein the frequency synthesizer generates a local oscillator (LO) signal having a frequency that is an n^th harmonic of a GPS processing clock signal, and the divider circuit synthesizes the GPS processing clock signal from the LO signal, and wherein a data acquisition clock signal for sampling a GPS RF signal received by the GPS front end is obtained by frequency-dividing the GPS processing clock signal, and wherein leakage of the n^th harmonic of the GPS processing clock signal into a path of the GPS RF signal is downconverted and rejected by an intermediate frequency (IF) bandpass filter having a predefined center frequency, located in the path of the GPS RF signal, and wherein a frequency of the GPS processing clock signal is at least twelve times hi her than the redefined center frequency of the IF bandpass filter.

7. The mobile phone of claim 6 where the GPS RF front end integrated circuit includes:

a signal input for receiving a 13 MHz reference signal;

a voltage controlled oscillator (VCO) having an input, the VCO providing the LO signal at a frequency of approximately 1536f_o;

a divide-by-4 prescaler having an output;

a selectable divider having an input from the output of the divided-by-4 prescaler;

an accumulator coupled to the input of the selectable divider, the accumulator comprising an overflow bit which provides a time averaged divide ratio of 30.21875 to control the selectable divider;

a first mixer and a second mixer for providing an image reject mixer function;

the IF filter having a first IF filter and a second IF filter, each of the first IF filter and the second IF filter having a center frequency of 4f_o and each of the first IF filter and the second IF filter having high attenuation near dc;

an IF combiner circuit to effect image rejection by phase shifting and summation;

a divide-by-8 counter to synthesize the GPS processing clock signal;

a divide-by-3 counter to synthesize a data acquisition clock signal;

a linear Automatic Gain Control (AGC) function; and

an A/D converter which provides a sampled, digital representation of the IF signal.

8. The mobile phone of claim 7 where the selectable divider of the GPS RF front end integrated circuit can be selected to perform a divide-by-30 function or a divide-by-31 function.

9. The mobile phone of claim 8 where the accumulator of the GPS RF front end circuit comprises at least 5 bits.

10. The mobile phone of claim 9 wherein the overflow bit of the accumulator of the GPS RF front end circuit controls the selection of the divide-by-30 function, or the divide-by-31 function of the selectable divider.

11. The mobile phone of claim 10 where the GPS processing clock signal generated by the of the GPS RF front end circuit has a frequency at a value of 48fo.

12. The mobile phone of claim 11 where the data acquisition signal has a frequency at a value of 16fo.

13. The mobile phone of claim 7 where the selectable divider of the GPS RF front end integrated circuit can be selected to perform a divide-by-15 function or a divide-by-16 function, wherein the selectable divider output is divided by an additional divide-by-2 counter.

14. The mobile phone of claim 13 where the accumulator of the GPS RF front end circuit comprises 6 bits.

15. The mobile phone of claim 14 wherein the overflow bit of the accumulator of the GPS RF front end circuit controls the selection of the divide-by-15 function, or the divide-by-16 function of the selectable divider.

16. The mobile phone of claim 15 where the GPS processing clock signal generated by the of the GPS RF front end circuit has a frequency at a value of 48fo.

17. The mobile phone of claim 16 where the data acquisition signal has a frequency at a value of 16fo.

18. The mobile phone of claim 6, where n=32.

19. The mobile phone of claim 6, wherein the frequency synthesizer comprises a fractional-N-synthesizer.