Interrupt-related circuits, systems, and processes

• US 7,934,036 B2
• Filed: 04/10/2008
• Issued: 04/26/2011
• Est. Priority Date: 05/10/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Conti, Gregory, Dahan, Franck
• Primary Examiner(s): Dang; Khanh
• Application Number:
  US12/100,534
• Publication Number:
  US 20090049220A1
• Time in Patent Office: 1,111 Days
• Field of Search: 710260-269, 710/322, 710/323, 714/34, 718/108
• US Class Current: 710/261
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An electronic interrupt circuit includes an interrupt-related input line, a security-related status input line, a context-related status input line, and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line.

Claims

1. An electronic interrupt circuit comprising:

an interrupt-related input line;

a security-related status input line;

a context-related status input line;

a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line; and

a plurality of enable lines and a logic circuitry having a first set of inputs respectively coupled to the plurality of enable lines and a second set of inputs respectively coupled to said plural interrupt-related output lines.

2. The electronic interrupt circuit claimed in claim 1 wherein said logic circuitry supplies a one-line logic output responsive to both said first set of inputs and said second set of inputs.

3. The electronic interrupt circuit claimed in claim 2 further comprising a reporting register bit coupled to receive said one-line logic output from said logic circuitry.

4. The electronic interrupt circuit claimed in claim 3 further comprising a coupling circuit having an input connected to said one-line logic output from said logic circuitry, said coupling circuit having an interrupt output line.

5. The electronic interrupt circuit claimed in claim 1 wherein said logic circuitry has a set of output lines and includes plural logic gate circuits, each having a first input connected to one of the enable lines and a second input connected to one of the interrupt-related output lines, the logic gate circuits each having an output line forming a different one of the set of output lines of the logic circuitry.

6. The electronic interrupt circuit claimed in claim 5 further comprising a reporting register having a bit field coupled to receive each said output line from said logic gate circuits.

7. The electronic interrupt circuit claimed in claim 1 further comprising an interrupt handler circuit having interrupt request inputs coupled to said plural interrupt-related output lines.

8. The electronic interrupt circuit claimed in claim 1 further comprising a processor having an interrupt-related output coupled to said interrupt-related input line.

9. The electronic interrupt circuit claimed in claim 8 wherein said processor has a security status output coupled to said security status input line.

10. The electronic interrupt circuit claimed in claim 8 further comprising a register coupled to said processor and to said context-related status input line.

11. The electronic interrupt circuit claimed in claim 1 wherein said interrupt-related input line is a wait for interrupt line.

12. The electronic interrupt circuit claimed in claim 1 wherein said conversion circuit includes an interrupt enabling register and an interrupt-generating circuit, responsive to said interrupt enabling register and to each of said plural interrupt-related output lines, to selectively generate at least one interrupt.

13. An electronic interrupt circuit comprising:

an interrupt-related input line;

a security-related status input line;

a context-related status input line;

a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line; and

register having a bit field for holding bits related to the state of activity of said plural interrupt-related output lines, a processor circuit, and an interrupt handler circuit coupling said plural interrupt-related output lines to said processor circuit, and said register is coupled separately to said processor circuit.

14. A process of manufacturing an electronic product, the process comprising:

preparing in integrated circuitry form an interrupt-related input line, a security related status input line, a virtual context-related status input line and a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line, wherein said plural interrupt-related output lines include a public nonvirtual interrupt output line, a secure nonvirtual interrupt output line, a public virtual interrupt output line, and a secure virtual interrupt output line.

15. An electronic interrupt circuit comprising:

an interrupt-related input line;

a security-related status input line;

a context-related status input line;

a conversion circuit having plural interrupt-related output lines and selectively operable in response to an interrupt-related signal on said interrupt-related input line depending on an active or inactive status of each of said security-related status input line and said context-related status input line; and

wherein said plural interrupt-related output lines include a public nonvirtual interrupt output line, a secure nonvirtual interrupt output line, a public virtual interrupt output line, and a secure virtual interrupt output line.