System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor
First Claim
1. A superscalar processor adapted to execute at least one instruction out of program order, said superscalar processor comprising:
- an instruction window that has a first storage location and a second storage location for storing instructions, an instruction stored in the second storage location being stored in the first storage location when an instruction stored in the first storage location is retired;
a plurality of functional units that execute an instruction out of program order;
a buffer that has storage locations at which an execution result of each instruction is stored;
register renaming circuitry that associates uniquely an address indicating a fixed storage location in the buffer with each instruction included at each storage location in the instruction window, regardless of a change in the storage location of the instruction in the instruction window;
a register array that includes a plurality of array locations referenced so that an execution result of a retired instruction can be provided to the referenced array location;
a retirement control block that determines whether an executed instruction can be retired or not; and
an instruction retirement unit that retires an instruction that can be retired by associating an execution result of each instruction that can be retired with an array location within the register array.
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Accused Products
Abstract
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
315 Citations
25 Claims
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1. A superscalar processor adapted to execute at least one instruction out of program order, said superscalar processor comprising:
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an instruction window that has a first storage location and a second storage location for storing instructions, an instruction stored in the second storage location being stored in the first storage location when an instruction stored in the first storage location is retired; a plurality of functional units that execute an instruction out of program order; a buffer that has storage locations at which an execution result of each instruction is stored; register renaming circuitry that associates uniquely an address indicating a fixed storage location in the buffer with each instruction included at each storage location in the instruction window, regardless of a change in the storage location of the instruction in the instruction window; a register array that includes a plurality of array locations referenced so that an execution result of a retired instruction can be provided to the referenced array location; a retirement control block that determines whether an executed instruction can be retired or not; and an instruction retirement unit that retires an instruction that can be retired by associating an execution result of each instruction that can be retired with an array location within the register array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer system having a processor and a memory adapted to store instructions having a program order, said processor comprising:
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an instruction window that has a first storage location and a second storage location for storing instructions, an instruction stored in the second storage location being stored in the first storage location when an instruction stored in the first storage location is retired; register renaming circuitry that associates uniquely an address indicating a fixed storage location in the buffer with each instruction included at each storage location in the instruction window, regardless of a change in the storage location of the instruction in the instruction window, said register renaming circuitry associating an address with at least one instruction in one clock cycle; a buffer coupled to the register renaming circuitry, said buffer storing an execution result of an instruction at a location described by an address associated with each instruction; a plurality of functional units coupled to the buffer, said plurality of functional units executing an instruction out of program order; an array having a plurality of locations each adapted to identify an execution result of a retiring instruction; a control block that determines whether an executed instruction can be retired; and an instruction retiring section coupled to the control block circuitry and the array, said instruction retiring section retiring an instruction that can be retired by associating an execution result of the instruction that can be retired with a location in the array, and allowing the execution results of the instructions that can be retired to be stored at respective particular locations of the array. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A superscalar processor for executing at least one instruction out of order, said superscalar processor comprising:
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an instruction window that has a first storage location and a second storage location for storing instructions, an instruction stored in the second storage location being stored in the first storage location when an instruction stored in the first storage location is retired; a buffer for storing an execution result of a first instruction among an instruction group and an execution result of a second instruction among an instruction group; a superscalar register renaming circuitry that associates, among a first address and a second address each of which indicates a fixed storage location in the buffer, the first address with the first instruction among the instruction group and the second address with the second instruction among the instruction group, regardless of a change in the storage location of the instruction in the instruction window, the first address associated with the first instruction indicating a first location of the buffer at which the execution result of the first instruction is stored, the second address associated with the second instruction indicating a second location of the buffer at which the execution result of the second instruction is stored; a plurality of functional units that execute the first instruction and the second instruction out of order among the instruction group; a register array that has a plurality of register array locations for storing an execution result of a retired instruction; a retirement control block that determines whether the first instruction can be retired and determines whether the second instruction can be retired; and an instruction retirement unit that retires the first instruction and the second instruction by storing the execution result of the first instruction stored in the first location of the buffer at a first register array location and storing the execution result of the second instruction stored in the second location of the buffer at a second register array location approximately simultaneously. - View Dependent Claims (22, 23, 24, 25)
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Specification