High-speed analog-to-digital conversion with improved robustness to timing uncertainty

• US 7,934,144 B2
• Filed: 11/12/2003
• Issued: 04/26/2011
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Quellan, Inc. (Renesas Electronics Corporation)
• Inventors: Bajekal, Sanjay, Ralph, Stephen E., Kim, Andrew Joo
• Primary Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US10/706,187
• Publication Number:
  US 20040105462A1
• Time in Patent Office: 2,722 Days
• Field of Search: 375/317, 375/341, 714/780
• US Class Current: 714/780
• CPC Class Codes: H03M 1/0675 using redundancy
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection

Abstract

A method and system using the principle of generalized maximum likelihood estimation to resolve sample timing uncertainties that are associated with the decoding of communication signals. By using generalized maximum likelihood estimation, sample timing uncertainty can be resolved by taking multiple samples of the received signal within a symbol period and determining which sample best corresponds to the optimal sample timing. The sample which best corresponds to the optimal sample timing can be determined from a timing index which can be calculated from ambiguity indicators that are based on the samples of the received signal.

Claims

1. A decoding unit for decoding a received signal comprising:

a plurality of soft-decoders, each soft-decoder operable to sample the received signal at a different time within a symbol period and to output two values for each sample, the first value comprising a preliminary decoded value and the second value comprising an ambiguity indicator; and

a logic device coupled to the each of the soft-decoders, for determining a decoded value for each symbol based on one or more preliminary decoded values and ambiguity indicators.

2. The decoding unit of claim 1, wherein the soft-decoders are substantially identical to one another.

3. The decoding unit of claim 1, wherein each soft-decoder comprises:

a first comparator with inputs comprising the received signal and a first reference voltage;

a second comparator with inputs comprising the received signal and a second reference voltage; and

a third comparator with inputs comprising the received signal and a third reference voltage.

4. The decoding unit of claim 1, wherein each soft-decoder comprises a plurality of comparators and one or more logical AND gates.

5. The decoding unit of claim 1, further comprising a plurality of delay elements coupled to the soft-decoders.

6. The decoding unit of claim 1, further comprising a plurality of delay elements coupled to the soft-decoders, each delay element delaying the received signal by a different amount.

7. The decoding unit of claim 1, further comprising a plurality of delay elements coupled to the soft-decoders, each delay element delaying a clock signal by a different amount.

8. A decoding unit for decoding a received signal comprising:

an asynchronous soft-decoder that continuously samples the received signal and produces a decoded output signal and an ambiguous indicator signal;

a plurality of first delay elements coupled to a first soft-decoder, each first delay element generating a different delay relative to another first delay element and producing an ambiguity indicator from the ambiguous indicator signal;

a plurality of second delay elements coupled to a second soft-decoder output, each second delay element generating a different delay relative to another second delay element and producing a preliminary decoded output from the decoded output signal; and

a logic device coupled to the each of the first and second delay elements, for determining a decoded value based on one or more of the preliminary decoded outputs and ambiguity indicators.

9. The decoding unit of claim 8, wherein the soft-decoder comprises:

a first comparator with inputs comprising the received signal and a first reference voltage;

a second comparator with inputs comprising the received signal and a second reference voltage; and

a third comparator with inputs comprising the received signal and a third reference voltage.

10. The decoding unit of claim 8, wherein the soft-decoder comprises a plurality of comparators and one or more logical AND gates.

11. A decoding unit for decoding a received signal comprising:

an analog-to-digital converter for sampling the received signal faster than once every symbol period of the received signal and outputting for each sample a first value comprising a preliminary decoded value and a second value comprising an ambiguity indicator; and

a processor coupled to the converter for grouping a subset of sampled first and second values derived from the single symbol period, for examining the subset of sampled first and second values and determining a first value closest to an optimum sampling time based on a principle of generalized maximum likelihood, for decoding the first value closest to the optimum sampling time and outputting that decoded first value as the decoded symbol.

12. The decoding unit of claim 11, further comprising a clock recovery unit coupled to the converter for providing a clock signal.

13. The decoding unit of claim 11, wherein the processor calculates the first value closest to the optimum sampling time by:

computing an absolute difference between each first value and a nearest level corresponding to a decoded symbol;

finding a first value which has a smallest absolute difference from the subset of first values; and

taking the first value with the smallest absolute difference as the first value closest to the optimum sampling time.

14. A method for decoding a received signal comprising:

receiving a signal;

estimating an optimal timing offset on a symbol-by-symbol basis; and

decoding the received signal using generalized maximum likelihood estimation with the estimated optimal timing offset,

wherein estimating an optimal timing offset on a symbol-by-symbol basis comprises generating an ambiguity indicator and a preliminary decoded value for a sample.

15. A method for decoding a received signal comprising:

receiving a signal;

estimating an optimal timing offset on a symbol-by-symbol basis; and

decoding the received signal using generalized maximum likelihood estimation with the estimated optimal timing offset,

wherein estimating an optimal timing offset on a symbol-by-symbol basis comprises;

dividing the received signal into a plurality of received signals; and

delaying each of the plurality of received signals by different amounts of time.

16. A method for decoding a received signal comprising:

receiving a signal;

estimating an optimal timing offset on a symbol-by-symbol basis; and

decoding the received signal using generalized maximum likelihood estimation with the estimated optimal timing offset,

wherein estimating an optimal timing offset on a symbol-by-symbol basis comprises;

determining a clock signal from the received signal;

taking multiple samples of the received signal in accordance with the clock signal; and

converting the received signal into the digital domain based on the multiple samples.

17. A method for decoding a received signal comprising:

receiving a signal;

estimating an optimal timing offset on a symbol-by-symbol basis; and

decoding the received signal using generalized maximum likelihood estimation with the estimated optimal timing offset,

wherein decoding the received signal using generalized maximum likelihood estimation with the optimal timing offset comprises determining a sample timing index from one or more ambiguity indicators.

18. A method for decoding a received signal comprising:

receiving a signal;

estimating an optimal timing offset on a symbol-by-symbol basis; and

decoding the received signal using generalized maximum likelihood estimation with the estimated optimal timing offset,

wherein decoding the received signal using generalized maximum likelihood estimation with the optimal timing offset comprises identifying a symbol that corresponds to a selected timing index.

19. The method of claim 18, wherein estimating an optimal timing offset on a symbol-by-symbol basis comprises:

dividing an ambiguity indicator signal and a preliminary decoded value signal derived from the received signal; and

delaying each ambiguity indicator signal and each preliminary decoded value signal by different amounts of time.