Method of forming shielded gate FET with self-aligned features

• US 7,935,561 B2
• Filed: 06/08/2009
• Issued: 05/03/2011
• Est. Priority Date: 09/20/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Park, Chanho
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US12/480,031
• Publication Number:
  US 20090246923A1
• Time in Patent Office: 694 Days
• Field of Search: 438/70, 438/FOR.192, 257/409, 257/508, 257/630, 257/E21.419
• US Class Current: 438/70
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for forming a shielded gate field effect transistor includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A shield electrode is formed in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric. A gate electrode recessed in each trench is formed over the shield electrode, the gate electrode being insulated from the shield electrode. Using a first mask, a body region of a second conductivity type is formed in the semiconductor region by implanting dopants. Using the first mask, source regions of the first conductivity type are formed in the body region by implanting dopants.

Claims

1. A method for forming a shielded gate field effect transistor, comprising:

forming trenches in a semiconductor region of a first conductivity type;

forming a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

forming a gate electrode recessed in each trench over the shield electrode, the gate electrode being insulated from the shield electrode;

using a first mask, forming a body region of a second conductivity type in the semiconductor region by implanting dopants; and

using the first mask, forming source regions of the first conductivity type in the body region by implanting dopants.

2. The method of claim 1 wherein when implanting dopants to form the body region, the first mask covers a top surface of the semiconductor region between adjacent trenches such that a substantial amount of the implant dopants enter the semiconductor region through upper trench sidewalls not covered by the recessed gate electrode.

3. The method of claim 1 wherein the trenches are formed using the first mask.

4. The method of claim 1 wherein a second mask is used in forming the trenches.

5. The method of claim 4 wherein the first mask comprises photoresist.

6. The method of claim 1 wherein the first mask comprises one of oxide, nitride, and a composite layer including nitride and oxide.

7. The method of claim 1 wherein the first mask is formed over a surface of the semiconductor region before the trenches are formed and is used to define the trenches.

8. The method of claim 1 wherein the first mask is formed over a surface of the semiconductor region after forming the trenches.

9. The method of claim 1 wherein a bottom boundary of the body region has a corrugated profile.

10. The method of claim 1 wherein a bottom of the body region is deepest at sidewalls of the trenches and shallowest at a midpoint between adjacent trenches.

11. The method of claim 1 further comprising:

prior to forming the gate electrode, forming a gate dielectric layer lining upper sidewalls of each trench and extending over the shield electrode, the gate dielectric layer being thinner than the shield dielectric.

12. The method of claim 1 further comprising:

prior to forming the gate electrode;

forming an inter-electrode dielectric layer extending over the shield electrode in each trench; and

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric.

13. The method of claim 1 wherein the step of forming a recessed gate electrode comprises:

filling the trenches with a conductive material; and

recessing the conductive material in the trenches so that upper sidewalls of the trenches are not covered by the conductive material.

14. The method of claim 1 further comprising:

removing the first mask;

forming a dielectric material in each trench over the gate electrode; and

forming an interconnect layer contacting the source regions and the body region.

15. The method of claim 1 wherein an implant energy in the range of about 150 KeV to about 220 KeV is used in forming the body region.

16. The method of claim 1 wherein the semiconductor region includes a silicon substrate and an epitaxial layer extending over the silicon substrate, and the trenches extend through the epitaxial layer and terminate in the silicon substrate.

17. The method of claim 1 wherein the semiconductor region includes a silicon substrate and an epitaxial layer extending over the silicon substrate, and the trenches terminate in the epitaxial layer.

18. The method of claim 1 wherein the semiconductor region comprises an epitaxial layer formed over a substrate of the second conductivity type to thereby form an IGBT.

19. The method of claim 1 wherein the body region is formed using a dual-pass angled implant.

20. The method of claim 1 wherein the source regions are formed using a dual-pass angled implant.

21. A method for forming a shielded gate field effect transistor (FET) comprising:

forming a mask over a semiconductor region of a first conductivity type, the mask having openings through which the semiconductor region is exposed;

forming trenches extending in the semiconductor region by recessing the semiconductor region through the mask openings;

forming a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

forming a gate electrode recessed in each trench over the shield electrode, the gate electrode being insulated from the shield electrode;

using the first mask, forming a body region of a second conductivity type in the semiconductor region by implanting dopants, the first mask covering a top surface of the semiconductor region between adjacent trenches such that a substantial amount of the implant dopants enter the semiconductor region through upper trench sidewalls not covered by the recessed gate electrode; and

using the first mask, forming source regions of the first conductivity type in the body region by implanting dopants.

22. The method of claim 21 wherein the mask comprises one of oxide, nitride, and a composite layer including nitride and oxide.

23. The method of claim 21 wherein a bottom boundary of the body region has a corrugated profile.

24. The method of claim 21 wherein a bottom of the body region is deepest at sidewalls of the trenches and shallowest at a midpoint between adjacent trenches.

25. The method of claim 21 further comprising:

prior to forming the gate electrode, forming a gate dielectric layer lining upper sidewalls of each trench and extending over the shield electrode, the gate dielectric layer being thinner than the shield dielectric.

26. The method of claim 21 further comprising:

prior to forming the gate electrode;

forming an inter-electrode dielectric layer extending over the shield electrode in each trench; and

forming a gate dielectric layer lining upper sidewalls of each trench, the gate dielectric layer being thinner than the shield dielectric.

27. The method of claim 21 wherein the step of forming a recessed gate electrode comprises:

filling the trenches with a conductive material; and

recessing the conductive material in the trenches so that the upper sidewalls of the trenches are not covered by the conductive material.

28. The method of claim 21 further comprising:

removing the mask;

forming a dielectric material in each trench over the gate electrode; and

forming an interconnect layer contacting the source regions and the body region.

29. The method of claim 21 wherein an implant energy in the range of about 150 KeV to about 220 KeV is used in forming the body region.

30. The method of claim 21 wherein the semiconductor region includes a silicon substrate and an epitaxial layer extending over the silicon substrate, and the trenches extend through the epitaxial layer and terminate in the silicon substrate.

31. The method of claim 21 wherein the semiconductor region includes a silicon substrate and an epitaxial layer extending over the silicon substrate, and the trenches terminate in the epitaxial layer.

32. The method of claim 21 wherein the semiconductor region comprises an epitaxial layer formed over a substrate of the second conductivity type to thereby form an IGBT.

33. The method of claim 21 wherein the body region is formed using a dual-pass angled implant.

34. The method of claim 21 wherein the source regions are formed using a dual-pass angled implant.