Electronic devices

• US 7,935,565 B2
• Filed: 12/12/2003
• Issued: 05/03/2011
• Est. Priority Date: 12/14/2002
• Status: Active Grant

• Current Assignee: FlexEnable Limited (Plastic Logic JSC)
• Original Assignee: Plastic Logic Limited (Plastic Logic JSC)
• Inventors: Mackenzie, John Devin, Brown, Thomas Meredith, Sirringhaus, Henning
• Primary Examiner(s): Graybill; David E
• Application Number:
  US10/538,857
• Publication Number:
  US 20060160276A1
• Time in Patent Office: 2,699 Days
• Field of Search: None
• US Class Current: 438/99
• CPC Class Codes: B05D 1/322 Removable films used as masks
• CPC Class Codes: B05D 3/145 After-treatment
• CPC Class Codes: B05D 5/12 to obtain a coating with specific electrical properties
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 30/00 Nanotechnology for materials or surface science, e.g. nanocomposites
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/471 the gate dielectric comprising only organic materials
• CPC Class Codes: H10K 10/472 the gate dielectric comprising only inorganic materials
• CPC Class Codes: H10K 10/491 Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes
• CPC Class Codes: H10K 71/221 by lift-off techniques
• CPC Class Codes: H10K 71/231 by etching of existing layers
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes
• CPC Class Codes: H10K 71/611 using printing deposition, e.g. ink jet printing
• CPC Class Codes: H10K 71/621 Providing a shape to conductive layers, e.g. patterning or selective deposition
• CPC Class Codes: H10K 71/821 Patterning of a layer by embossing, e.g. stamping to form trenches in an insulating layer
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/1135 Polyethylene dioxythiophene [PEDOT]; Derivatives thereof
• CPC Class Codes: H10K 85/115 Polyfluorene; Derivatives thereof
• CPC Class Codes: H10K 85/151 : Copolymers
• CPC Class Codes: Y10S 977/887 : Nanoimprint lithography, i.e. nanostamp

Abstract

A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.

Claims

1. A method for forming an electronic device having a multilayer structure, comprising:

embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate;

treating the surface of the substrate with a surface modification process that has a different effect on depressed regions of the substrate relative to non-depressed regions of the substrate, whereby the non-depressed regions and the depressed regions are given different surface energies, such that the deposition of a material is defined by the surface energy of the substrate in the first and second regions

depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the first and second electrodes are electrically insulated from each other by the third region; and

wherein the third region is a ridge wherein the ridge has a width that defines a length of a channel of the electronic device.

2. A method as claimed in claim 1, wherein the third region has a width defined by a depth to which embossing is performed.

3. A method as claimed in claim 2, wherein the step of embossing is performed with a tool having an embossing surface, the embossing surface of the tool bearing at least one protruding portion having a sharp protruding tip wherein the protruding portion has a width that widens from the sharp protruding tip, towards the embossing surface of the tool such that the width of a depressed region of the substrate, as measured in a plane of the surface of the substrate, is dependent on a depth to which the at least one protruding portion of the tool enters into the substrate.

4. A method as claimed in claim 2, wherein the step of embossing is performed with a tool having an embossing surface, the embossing surface of the tool bearing at least one recessed portion having a recessed point wherein the recessed portion has a width that widens from the recessed point, towards the embossing surface of the tool such that a raised region of the substrate has a width, as measured in a plane of the surface of the substrate, that is dependent on a depth to which the embossing surface of the tool enters into the substrate.

5. A method as claimed in claim 1, wherein a cross section of the ridge is substantially rectangular.

6. A method as claimed in claim 1, wherein a cross section of the ridge is substantially triangular.

7. A method as claimed in claim 1, wherein the embossing step is performed at a temperature within 50°

C. of the glass transition temperature of a topmost surface of the substrate.

8. A method as claimed in claim 1, wherein the embossing step is performed at a temperature at which a topmost surface of the substrate is in a liquid phase.

9. A method as claimed in claim 1, wherein the substrate comprises a flexible plastic substrate such as poly(ethyleneterephthalate) (PET), polyethersulphone (PES) or polyethernaphthalene (PEN).

10. A method as claimed in claim 1, wherein the substrate comprises a rigid substrate coated with a polymer layer.

11. A method as claimed in claim 1, wherein said substrate comprises a polar polymer layer as the substrate.

12. A method as claimed in claim 1, wherein said treating step comprises exposing the substrate to one or more of an oxygen plasma, carbon-tetrafluoride plasma, ultra-violet or ozone surface treatment.

13. A method as claimed in claim 1, wherein said treating step comprises depositing a surface modifying layer onto the substrate at an oblique angle such that the surface modifying material is deposited onto the non-depressed portions of the substrate, and the depressed portions are shadowed by the non-depressed portions during the deposition of the surface modifying layer.

14. A method as claimed in claim 1, wherein said treating step comprises exposing the substrate to a physical etching method such as reactive ion etching.

15. A method as claimed in claim 1, wherein said treating step comprises applying a flat stamp to the surface.

16. A method as claimed in claim 15, wherein the flat stamp is inked with a self-assembled monolayer.

17. A method as claimed in claim 16, wherein the self-assembled monolayer is capable of bonding with functional groups on the surface of the substrate.

18. A method as claimed in claim 16, wherein the self-assembled monolayer is octyltrichlorosilane or fluoroalkyltrichlorosilane.

19. A method as claimed in claim 16, wherein the self-assembled monolayer comprises a methoxy silane.

20. A method as claimed in claim 1, wherein the solution of conductive or semiconductive material comprises a conductive ink.

21. A method as claimed in claim 20, wherein the conductive ink comprises a conductive polymer.

22. A method as claimed in claim 21, wherein the conductive polymer is polyethylenedioxythiophene doped with polystyrene sulfonic acid (PEDOT/PSS).

23. A method as claimed in claim 20, wherein the conductive ink comprises a conductive inorganic dispersion of electrically conductive nanoparticles.

24. A method as claimed in claim 1, further comprising the step of depositing a layer of semiconductive material over the substrate and first and second electrodes.

25. A method as claimed in claim 24, wherein the semiconductive material formed over the substrate and first and second electrodes is regioregular poly(3-hexylthiophene) (P3HT) or poly(dioctylfluorene-co-bithiophene) (F8T2).

26. A method as claimed in claim 24, wherein the semiconductive material formed over the substrate and first and second electrodes is an inorganic nanoparticulate or an inorganic nanowire semiconductor.

27. A method as claimed in one of claims 24 to 26, further comprising the step of depositing a layer of dielectric over the layer of semiconductive material.

28. A method as claimed in claim 27, wherein the layer of dielectric comprises a polymer layer.

29. A method as claimed in claim 28, wherein the polymer layer is poly(methylmethacrylate) (PMMA).

30. A method as claimed in claim 26, further comprising the step of printing a pattern of conductive material to form an electrode for said electronic device.

31. A method as claimed in claim 30, wherein the electrode is formed from a conductive polymer or an inorganic material.

32. A method as claimed in claim 1, wherein the electronic device is a transistor.

33. A method as claimed in claim 1, wherein conductive material is deposited on the substrate which forms source and drain electrodes of the electronic device.

34. A method as claimed in claim 27, wherein the layer of dielectric deposited over the semiconductive layer is a gate dielectric layer.

35. A method as claimed in claim 34, further comprising the step of depositing a gate electrode onto the surface of the gate dielectric layer.

36. A method as claimed in claim 1, wherein the embossing step is performed with a tool having an embossing surface suitable for embossing the substrate, the embossing surface bearing an array of protruding features with sharp tips.

37. A method as claimed in claim 36, wherein the sharp tips have a radius of curvature of less than 100 μ

m.

38. A method as claimed in claim 36, wherein the sharp tips have a radius of curvature of less than 10 μ

m.

39. A method as claimed in claim 36, wherein the protruding features have a rectangular profile.

40. A method as claimed in claim 1, wherein the third region has a width of less than 20 μ

m.

41. A method as claimed in claim 1, wherein the third region has a width of less than 5 μ

m.

42. A method as claimed in claim 1, wherein the third region has a width of less than 1 μ

m.

43. A method as claimed in claim 1, wherein the substrate comprises a functional layer of the electronic device, wherein the functional layer comprises one of a conducting material and a semiconducting material.

44. A method as claimed in claim 1, wherein the first and second electrodes are source and drain electrodes of a transistor.