Integrated passive device with a high resistivity substrate and method for forming the same

• US 7,935,607 B2
• Filed: 04/09/2007
• Issued: 05/03/2011
• Est. Priority Date: 04/09/2007
• Status: Expired due to Fees

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Cotronakis, James G., Daly, Terry K., Fender, Jason R., Abrokwah, Jonathan K., Reyes, Adolfo G., Costello, Keri L.
• Primary Examiner(s): Lee; Hsien-ming
• Assistant Examiner(s): PARENDO, KEVIN A
• Application Number:
  US11/733,063
• Publication Number:
  US 20080246114A1
• Time in Patent Office: 1,485 Days
• Field of Search: 438/381, 257/E27.01
• US Class Current: 438/381
• CPC Class Codes: H01L 27/016 Thin-film circuits

Abstract

According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).

Claims

1. A method of forming an integrated passive device (IPD) comprising:

forming an oxide layer having a thickness of at least 4 micrometers over a silicon substrate, said formation of the oxide layer occurring at a temperature that is less than 550°

C., wherein the oxide layer comprises tetraethyl orthosilicate (TEOS) oxide;

forming a plurality of passive electronic components over the oxide layer, wherein the plurality of passive electronic components jointly form a harmonic filter; and

forming a passivation layer over the oxide layer and the plurality of passive electronic components.

2. The method of claim 1, further comprising installing the IPD in a computing system.

3. The method of claim 2, wherein the passivation layer comprises silicon nitride.

4. The method of claim 3, wherein the thickness of the oxide layer is between approximately 4 and 6 micrometers.

5. The method of claim 4, wherein the silicon substrate has a thickness of between approximately 25 and 800 micrometers and a resistivity of greater than 1000 ohm-cm.

6. A method of forming an integrated passive device (IPD) comprising:

forming an oxide layer having a thickness of at least 4 micrometers over a silicon substrate, said formation of the oxide layer occurring at a temperature that is less than 550°

C., wherein the oxide layer comprises tetraethyl orthosilicate (TEOS) oxide;

forming a plurality of passive electronic components over the oxide layer, wherein the plurality of passive electronic components comprises a capacitor, a resistor, an inductor, or a combination thereof, and wherein the plurality of passive electronic components jointly form a harmonic filter; and

forming a passivation layer over the oxide layer and the plurality of passive electronic components.

7. The method of claim 6, wherein said formation of the oxide layer occurs at a temperature that is between approximately 150°

C. and 450°

C.

8. A method for forming an integrated passive device (IPD) comprising:

providing a silicon substrate with a resistivity that is greater than 1000 ohm-cm;

forming a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of at least 4micrometers over the silicon substrate, wherein forming the TEOS oxide layer occurs at a temperature that is less than 550°

C.;

forming a plurality of passive electronic components over the TEOS oxide layer after forming the TEOS oxide layer, wherein the plurality of passive electronic components jointly form a harmonic filter; and

forming a passivation layer over the plurality of passive electronic components and the TEOS oxide layer after forming the plurality of passive electronic components.

9. The method of claim 8, wherein the passivation layer comprises silicon nitride.

10. The method of claim 9, wherein the plurality of passive electronic components comprises a capacitor, a resistor, an inductor, or a combination thereof, and wherein forming the plurality of passive electronic components comprises:

forming a first conductive layer over the TEOS oxide layer; and

forming a second conductive layer over the first conductive layer.

11. The method of claim 10, wherein the temperature is between approximately 150°

C. and 450°

C.

12. The method of claim 11, wherein the silicon substrate has a thickness of between approximately 25 and 625 micrometers and the thickness of the TEOS oxide layer is between approximately 4 and 6 micrometers.

13. A microelectronic assembly comprising:

a silicon substrate with a resistivity of at least 1000 ohm-cm;

a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of at least 4 micrometers formed over the silicon substrate;

a plurality of passive electronic components formed over the TEOS oxide layer, wherein the plurality of passive electronic components jointly form a harmonic filter; and

a passivation layer formed over the TEOS oxide layer and the plurality of passive electronic components to provide protection from environmental elements.

14. The microelectronic assembly of claim 13, wherein the thickness of the TEOS oxide layer is between 4 and 6 micrometers.

15. The microelectronic assembly of claim 14, wherein the plurality of passive electronic components comprises a capacitor, a resistor, an inductor, or a combination thereof.

16. The microelectronic assembly of claim 15, further comprising an integrated circuit coupled to the plurality of passive electronic components.

17. The microelectronic assembly of claim 13, wherein the passivation layer comprises silicon nitride.