Polarity dependent switch for resistive sense memory

• US 7,935,619 B2
• Filed: 05/05/2010
• Issued: 05/03/2011
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Lu, Yong, Jung, Chulmin, Kim, Young Pil, Khoury, Maroun Georges
• Primary Examiner(s): Mandala; Victor
• Assistant Examiner(s): Moore; Whitney
• Application Number:
  US12/774,018
• Publication Number:
  US 20100210095A1
• Time in Patent Office: 363 Days
• Field of Search: 257/163, 257/213, 257/536, 257/379, 257/298, 257/156, 257/297, 257/164, 257/E21.346, 257/E21.389, 257/E21.703, 257/E27.079, 257/E27.112, 257/E29.211, 438/133, 438135-140, 438/514, 438/525, 365/148, 365/189.07, 365/189.16, 365/185.05
• US Class Current: 438/514
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H10B 61/20 comprising components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

Claims

1. A method of forming a memory unit comprising;

implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor; and

electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

2. A method according to claim 1, wherein the implanting step comprises halo implanting a dopant material in the source contact and not in the bit contact.

3. A method according to claim 1, wherein during the implantation step the bit contact is masked with a photoresist layer.

4. A method according to claim 1, wherein the implanting dopant material more heavily in a source contact than a bit contact comprises implanting dopant material at an angle of less than 90 degrees relative to a major surface of the substrate.

5. A method according to claim 1, wherein the implanting step comprises implanting a first amount of dopant material in the source contact and implanting a second amount of dopant material in the bit contact and the first amount is greater than the second amount.

6. A method according to claim 1, wherein the implanting step comprises implanting boron in the source contact and not in the bit contact.

7. A method according to claim 1, wherein the implanting step comprises forming a lightly doped drain region in the bit contact.

8. A method according to claim 2, wherein the implanting step comprises forming a lightly doped drain region in the bit contact.

9. A method according to claim 8, wherein the implanting step comprises forming a lightly doped drain region in the bit contact and the bit contact is not halo implanted.

10. A method according to claim 1, wherein the electrically connecting step comprises electrically connecting a spin-torque transfer memory cell to the bit contact.

11. A method according to claim 1, further comprising applying a write current in an easy direction through the source contact before the bit contact.

12. A method according to claim 11, further comprising applying a write current in a hard direction through the bit contact before the source contact.

13. A method according to claim 3, wherein during the implantation step the bit contact is masked with a photoresist layer while halo implanting a dopant material in the source contact and not in the bit contact.

14. A method of forming a memory unit comprising;

asymmetrically implanting more dopant material in a source contact than a bit contact of a semiconductor transistor; and

electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.

15. A method according to claim 14, wherein the asymmetrically implanting step comprises halo implanting a dopant material in the source contact and not in the bit contact.

16. A method according to claim 14, wherein during the asymmetrically implanting step the bit contact is masked with a photoresist layer.

17. A method according to claim 14, wherein the asymmetrically implanting step comprises implanting dopant material at an angle of less than 90 degrees relative to a major surface of the substrate.

18. A method according to claim 14, wherein the asymmetrically implanting step comprises forming a lightly doped drain region in the bit contact.

19. A method according to claim 14, wherein the electrically connecting step comprises electrically connecting a spin-torque transfer memory cell to the bit contact.

20. A method of forming a memory unit comprising;

implanting a halo dopant material more heavily in a source contact than a bit contact of a semiconductor transistor and forming a lightly doped drain region in the bit contact; and

electrically connecting a resistive sense memory cell to the bit contact, the resistive sense memory cell configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell.