Semiconductor device structure having enhanced performance FET device

• US 7,935,993 B2
• Filed: 12/21/2009
• Issued: 05/03/2011
• Est. Priority Date: 01/10/2006
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Chen, Xiangdong
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): TRICE, KIMBERLY N
• Application Number:
  US12/643,482
• Publication Number:
  US 20100096673A1
• Time in Patent Office: 498 Days
• Field of Search: 257/288
• US Class Current: 257/288
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.

Claims

1. A semiconductor device structure comprising:

a field effect transistor device including a substrate, the transistor device being of an n-conductive type and including a gate stack on the substrate, the gate stack being provided with sidewall layers and sidewall spacers;

a stress film disposed on the spacers, the spacers and the stress film forming a trench, said trench extending below an upper surface of a gate electrode of the gate stack and exposing a vertical wall of said sidewall layers; and

a stress material disposed in the trench, so that a tensile stress resulting in the channel of the field effect transistor is increased, and wherein a portion of the stress material directly contacts said vertical wall of said sidewall layers.

2. The structure as claimed in claim 1, wherein said stress film is a tensile stress film and said stress material is a compressive stress material.

3. The structure as claimed in claim 1, wherein said stress film is a compressive stress film and said stress material is a tensile stress material.

4. The structure as claimed in claim 1, wherein the trench has a rectangular area.

5. The structure as claimed in claim 1, wherein the sidewall layers are oxide layers.

6. The structure as claimed in claim 1, wherein the gate stack has a height, and wherein the trench extends a distance approximately 50% along said height.

7. A semiconductor device structure comprising:

a pFET device including a substrate, the pFET device including a gate stack provided on the substrate, the gate stack being provided with sidewall layers and sidewall spacers;

a stress film disposed on the sidewall spacers, the sidewall spacers and the stress film forming a trench, said trench extending below an upper surface of a gate electrode of the gate stack and exposing a vertical wall of said sidewall layers; and

a stress material disposed in the trench, so that a compressive stress resulting in the channel of the pFET device is increased, and wherein a portion of the stress material directly contacts said vertical wall of said sidewall layers.