Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array

• US 7,936,000 B2
• Filed: 04/02/2009
• Issued: 05/03/2011
• Est. Priority Date: 08/30/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Srinivasan, Anand, Burke, Robert J., Tang, Sanh D.
• Primary Examiner(s): Ngo; Ngan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US12/417,128
• Publication Number:
  US 20090207649A1
• Time in Patent Office: 761 Days
• Field of Search: 257/302, 257/306, 257/202, 257/296, 257/329, 257/263, 257/E29.274, 257/E27.07, 257/E29.343, 365/149, 365/230.08, 365/189.05
• US Class Current: 257/302
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by a process in which source, drain and channel regions of the transistor are automatically defined and aligned by the fabrication process, without photolithographic patterning.

Claims

1. A DRAM array, comprising:

a substrate;

M polysilicon digit lines formed in the substrate, wherein M is a positive integer;

an M×

N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor comprises;

a polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion,

a first source/drain region defined in the top portion of the pillar,

a transistor channel region defined in the central portion of the pillar,

a second source/drain region defined in the bottom portion of the pillar,

a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region,

a transistor gate surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor, and

a spacer layer formed around only the top portion of the pillar and the first source/drain region;

N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column; and

M×

N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor.

2. The DRAM array according to claim 1, wherein the digit lines have been silicided.

3. The DRAM array according to claim 1, wherein the thickness of the respective transistor gate of each transistor corresponds with the thickness of the spacer layer.

4. The DRAM array according to claim 1, wherein each capacitor is a container capacitor.

5. The DRAM array according to claim 4, wherein a bottom cell plate of each capacitor directly contacts a top end of the pillar of the respective transistor.

6. The DRAM array according to claim 4, wherein a top cell plate opposing a bottom cell plate of each capacitor is formed as a common top cell plate to all of the capacitors.

7. The DRAM array according to claim 4, wherein the capacitors are single-sided container capacitors.

8. The DRAM array according to claim 4, wherein the capacitors are double-sided container capacitors.

9. A DRAM memory device, comprising:

a memory cell array containing M×

N cells for storing data signals of memory information, wherein each memory cell comprises;

a substrate,

M polysilicon digit lines formed in the substrate, wherein M is a positive integer,

an M×

N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor includes

a polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion,

a first source/drain region defined in the top portion of the pillar,

a transistor channel region defined in the central portion of the pillar, and

a second source/drain region defined in the bottom portion of the pillar,

a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, and

a transistor gate completely surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor,

N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column, and

M×

N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor;

a row and column address buffer for receiving external address signals for selecting a memory cell;

a row decoder;

a column decoder, wherein the row decoder and the column decoder together designate the selected memory cell by decoding the address signals;

a sense refresh amplifier for amplifying and reading a signal stored in the designated memory cell;

a data-in buffer for inputting data;

a data-out buffer for outputting data; and

a clock generator for generating a clock signal.

10. A computer system, comprising:

a processor; and

at least one semiconductor memory device coupled to exchange data with the processor via at least one memory bus, each memory device comprising

a memory cell array containing M×

N cells for storing data signals of memory information, wherein each memory cell comprises

a substrate,

M polysilicon digit lines formed in the substrate, wherein M is a positive integer,

an M×

N array of vertical transistors formed on the plurality of digit lines, wherein N is a positive integer and N transistors are formed on each digit line and are aligned with the transistors formed on adjacent rows to define N columns of transistors, and wherein each transistor includes

a polysilicon pillar epitaxially grown from one of the polysilicon digit lines, the pillar having a top end, a top portion, a central portion, and a bottom portion,

a first source/drain region defined in the top portion of the pillar,

a transistor channel region defined in the central portion of the pillar, and

a second source/drain region defined in the bottom portion of the pillar,

a dielectric layer formed on and surrounding the central portion of the pillar in alignment with the transistor channel region, and

a transistor gate completely surrounding the central portion of the pillar with the dielectric layer between the transistor gate and the pillar, the transistor gate being aligned with the channel region of the transistor,

N conductive paths formed of the same material as the transistor gates, wherein each conductive path connects the transistor gates along a respective column, and is formed as an extension of the transistor gates along the column, and

M×

N capacitors, wherein each capacitor is stacked on the top end of the pillar of a respective transistor;

a row and column address buffer for receiving external address signals for selecting a memory cell;

a row decoder;

a column decoder, wherein the row decoder and the column decoder together designate the selected memory cell by decoding the address signals;

a sense refresh amplifier for amplifying and reading a signal stored in the designated memory cell;

a data-in buffer for inputting data;

a data-out buffer for outputting data; and

a clock generator for generating a clock signal.