Nonvolatile semiconductor memory device and manufacturing method thereof

• US 7,936,004 B2
• Filed: 01/18/2007
• Issued: 05/03/2011
• Est. Priority Date: 03/27/2006
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sato, Mitsuru, Fukuzumi, Yoshiaki, Katsumata, Ryota, Kito, Masaru, Aochi, Hideaki, Kidoh, Masaru, Tanaka, Hiroyasu, Matsuoka, Yasuyuki, Nitayama, Akihiro
• Primary Examiner(s): Jackson, Jr.; Jerome
• Assistant Examiner(s): Chen; Yu
• Application Number:
  US11/654,551
• Publication Number:
  US 20070252201A1
• Time in Patent Office: 1,566 Days
• Field of Search: 257/324, 257/326, 257/328, 257/329, 257/E27.103, 365/184, 365/185.18, 365/185.28, 365/185, 365/17
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device includes a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; a second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory string and the first to nth electrodes of at least two other memory strings which are adjacent to the memory string in two directions are shared as first to nth conductor layers spread in two dimensions.

Claims

1. A nonvolatile semiconductor memory device comprising a plurality of memory strings arranged in a matrix shape in a row direction and a column direction, the plurality of memory strings including at least one memory string having a plurality of electrically programmable memory cells connected in series,

wherein the at least one memory string of the plurality of memory strings comprises a pillar shaped semiconductor, a first insulation film formed around the pillar shaped semiconductor, a charge storage layer formed around the first insulation film, a second insulation film formed around the charge storage layer, and first to nth electrodes formed around the second insulation film (n is a natural number not less than 2);

and

wherein the first to the nth electrodes of the at least one memory string are shared with a second memory string adjacent to the at least one memory string in the column direction and a third memory string adjacent to the at least one memory string in the row direction.

2. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth electrodes spread in two dimensions are plate-shaped conductor layers, respectively.

3. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the plurality of memory strings are arranged within a plane being vertical to the pillar shaped semiconductor with a matrix shape.

4. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth electrodes spread in two dimensions are stacked via an insulation film, respectively, and each of the plurality of memory strings is arranged in the first to the nth conductor layers spread in two dimensions with an array shape, respectively.

5. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer is an insulation film.

6. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first insulation film is a silicon oxide film, wherein the charge storage layer is a silicon nitride layer, and wherein the second insulation film is a silicon oxide film.

7. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shape semiconductor is either a cylindrical shape or a prism shape.

8. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shape semiconductor is formed vertically on a semiconductor substrate.

9. The nonvolatile semiconductor memory device as claimed in claim 1, wherein exterior edges of the electrodes forming the first to the nth electrodes of the at least one memory string are stepwise formed.

10. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer is located between the pillar shape semiconductor and the first to the nth electrodes of the at least one memory string.

11. The nonvolatile semiconductor memory device as claimed in claim 10, wherein the charge storage layer is a conductor layer.

12. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the memory device including the at least one memory string of the plurality of memory strings further comprises a first transistor connected to one end of the pillar shaped semiconductor and a second transistor connected to the other end of the pillar shaped semiconductor.

13. The nonvolatile semiconductor memory device as claimed in claim 12, wherein a source region of the first transistor is an n-type and the source region is directly connected to an n+ diffusion layer of a semiconductor substrate.

14. The nonvolatile semiconductor memory device as claimed in claim 13, further comprising:

a poly-silicon layer on the n+ diffusion layer of the semiconductor substrate,

wherein the pillar shaped semiconductor is connected to both of the poly-silicon and the n+ diffusion layer.

15. The nonvolatile semiconductor memory device as claimed in claim 12, wherein a source region of the first transistor is an p-type and the source region is directly connected to a p+ diffusion layer of a semiconductor substrate.

16. The nonvolatile semiconductor memory device as claimed in claim 12, the at least one memory string further comprising a source region, wherein the source region of the at least one memory string is electrically connected to the first transistor.

17. The nonvolatile semiconductor memory device as claimed in claim 1, the memory device further comprising a first transistor and another transistor, wherein a gate electrode of the first transistor coupled to the at least one memory string and a gate electrode of the another transistor coupled to another one of the plurality of memory strings are formed from a shared conductor layer.

18. The nonvolatile semiconductor memory device as claimed in claim 1, wherein a memory transistor area includes the plurality of memory strings and another memory transistor area includes the plurality of memory strings, and the areas are electrically insulated by an interlayer insulation film.

19. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the pillar shaped semiconductor is n-type semiconductor.

20. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the plurality of the memory cells is a depletion type transistor.

21. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the charge storage layer has a film including nano-crystal.

22. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the plurality of memory strings have a symmetry shape to a center axis of the pillar shaped semiconductor.

23. The nonvolatile semiconductor memory device as claimed in claim 1, wherein the first to the nth electrodes of the at least one memory string forms word lines, respectively, and wherein the first to the nth electrodes of the at least one memory string are driven by a word line driving circuit, respectively.

24. The nonvolatile semiconductor memory device as claimed in claim 1, wherein bit lines respectively connected to a drain electrode of the plurality of memory strings are connected to a sense amplifier.

25. The nonvolatile semiconductor memory device as claimed in claim 1, wherein a fourth insulation film is formed between the first to the nth electrodes of the at least one memory string of the plurality of memory strings, and wherein exterior edges of the first to nth electrodes of the at least one memory string and an exterior edge of the fourth insulation film are stepwise formed.

26. The nonvolatile semiconductor memory device as claimed in claim 1, wherein a fourth insulation film is formed between the first to the nth electrodes of the memory strings, and wherein the parts of the edges of the first to the nth electrodes of the memory strings and the edge of the fourth insulation film are stepwise formed, and the other parts of the edges of the first to nth electrodes of the memory strings and the edge of the fourth insulation film are not stepwise formed.