Semiconductor device with backfilled isolation

• US 7,936,006 B1
• Filed: 10/06/2005
• Issued: 05/03/2011
• Est. Priority Date: 10/06/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Gitlin, Daniel, Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): SNOW, COLLEEN ERIN
• Application Number:
  US11/244,566
• Time in Patent Office: 2,035 Days
• Field of Search: 257/288, 257/339, 257/626, 257/243, 257/327, 257/336, 257/344, 257/616, 257/E29.012, 257/E29.278, 257/E29.435, 257/E29.266, 257/E29.269, 257/E21.435, 438/197, 438/299, 438/300, 438/163, 438/174, 438/175, 438/194, 438/196, 438/282, 438/289, 438/290, 438/339
• US Class Current: 257/327
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.

Claims

1. A metal-oxide-semiconductor (“

MOS”

) device comprising;

a gate electrode having sidewalls;

a first sidewall spacer extending from the gate electrode toward a source region;

a second sidewall spacer extending from the gate electrode toward a drain region;

a source extension extending at least partially beneath the first sidewall spacer;

a drain extension extending at least partially beneath the second sidewall spacer;

a body;

a channel portion;

a first embedded dielectric structure extending at least partially beneath the source extension;

a second embedded dielectric structure extending at least partially beneath the drain extension; and

a web disposed between the first embedded dielectric structure and the second embedded dielectric structure, the web connecting the channel portion to the body, wherein a portion of at least one of the first embedded dielectric structure and the second embedded dielectric structure extends directly below an area defined by the channel portion toward the web and between the channel portion and the body.

2. The MOS device of claim 1 wherein the source extension comprises a first lightly-doped region and the drain extension comprises a second lightly-doped region.

3. The MOS device of claim 1 wherein each of the first embedded dielectric structure and the second embedded dielectric structure comprises dielectric material applied to the MOS device in a fluid form.

4. The MOS device of claim 1 further comprising a halo region, wherein the embedded dielectric structure is proximate to at least one of the source extension and the drain extension, and is also proximate to the halo region.

5. The MOS device of claim 1 wherein each of the first embedded dielectric structure and the second embedded dielectric structure comprises low-k dielectric material.

6. A field programmable gate array having a MOS device according to claim 1.

7. A metal-oxide-semiconductor (“

MOS”

) device comprising;

a gate electrode having sidewalls;

a first sidewall spacer extending from the gate electrode toward a source region;

a second sidewall spacer extending from the gate electrode toward a drain region;

a source extension extending at least partially beneath the first sidewall spacer;

a drain extension extending at least partially beneath the second sidewall spacer;

a body;

a channel;

at least a portion of an embedded dielectric structure extending from the source region toward the drain region directly below an area defined by a first portion of the channel and between the first portion of the channel and the body, wherein a remaining portion of the channel connects the channel to the body so as to avoid floating body effect.

8. The MOS device of claim 7 wherein the remaining portion of the channel is at a first end of the channel.

9. The MOS device of claim 8 further comprising a second remaining portion of the channel connecting the channel to the body at a second end of the channel.

10. The MOS device of claim 7 wherein the embedded dielectric structure comprises low-stress dielectric material.

11. The MOS device of claim 7 wherein the embedded dielectric structure comprises porous dielectric material.

12. A method of fabricating a metal-oxide-semiconductor (“

MOS”

) device comprising;

forming a gate electrode having sidewalls with a first sidewall spacer extending from the gate electrode toward a source region and a second sidewall spacer extending from the gate electrode toward a drain region, a source extension extending at least partially beneath the first sidewall spacer and a drain extension extending at least partially beneath the second sidewall spacer;

forming first recesses to a first selected depth in the source region and in the drain region of the MOS device;

forming a source spacer and a drain spacer;

forming a first reentrant recess in the source region and a second reentrant recess in the drain region;

filling the first reentrant recess and the second reentrant recess with dielectric material;

removing excess dielectric material so as to form at least one embedded dielectric structure, wherein at least a portion of the at least one embedded dielectric structure extends from the source region toward the drain region directly below an area defined by a first portion of a channel and between the first portion of the channel and a body, wherein a remaining portion of the channel connects the channel to the body so as to avoid floating body effect;

removing the source spacer and the drain spacer; and

filling remaining portions of the first reentrant recess, the second reentrant recess, and the first recesses with contact material.

13. The method of claim 12 wherein the dielectric material is a low-stress dielectric material.

14. The method of claim 12 wherein the step of filling the first reentrant recess and the second reentrant recess with dielectric material comprises applying a fluid.

15. The method of claim 14 wherein the step of filling the first reentrant recess and the second reentrant recess with dielectric material further comprises curing the fluid to form a porous dielectric material.

16. The method of claim 12 wherein the first selected depth is greater than a depth of a halo implant.

17. The method of claim 12 further comprising steps, after the step of filling remaining portions of the first reentrant recess, the second reentrant recess, and the first recesses with contact material, of:

implanting dopant into the contact material so as to form a lightly doped drain region and a lightly doped source region;

forming gate sidewall spacers over a portion of source contact material and over a portion of drain contact material; and

implanting dopant into the source contact material so as to form a source contact and into the drain contact material so as to form a drain contact.