I/O buffer with low voltage semiconductor devices
First Claim
1. A method for protection from an over-voltage condition in an input/output (“
- I/O”
) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is coupled to a second over-voltage protection circuit, comprising;
a) generating first and second bias voltages from an operating voltage of the buffer;
b) generating a third bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer;
c) generating a fourth bias voltage from either i) the second bias voltage, or ii) the output signal voltage of the buffer;
d) providing the third and fourth bias voltages to the first and second over-voltage protection circuits, respectively;
e) preventing, by the first over-voltage protection circuit, the over-voltage condition on at least the first I/O transistor, wherein the first I/O transistor comprises a P-channel PET, and the first over-voltage protection circuit comprises a first over-voltage protection transistor and a second over-voltage protection transistor, wherein the first and second over-voltage protection transistors comprise P-channel field effect transistors (FETs), andf) preventing, by the second over-voltage protection circuit, the over-voltage condition on at least the second I/O transistor, wherein the second I/O transistor comprises an N-channel FET, and the second over-voltage protection circuit comprises (i) a third over-voltage protection transistor and (ii) a fourth over-voltage protection transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs,wherein the over-voltage condition comprises at least one of a DC and a transient over-voltage condition, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms.
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Accused Products
Abstract
Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
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Citations
14 Claims
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1. A method for protection from an over-voltage condition in an input/output (“
- I/O”
) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is coupled to a second over-voltage protection circuit, comprising;a) generating first and second bias voltages from an operating voltage of the buffer; b) generating a third bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer; c) generating a fourth bias voltage from either i) the second bias voltage, or ii) the output signal voltage of the buffer; d) providing the third and fourth bias voltages to the first and second over-voltage protection circuits, respectively; e) preventing, by the first over-voltage protection circuit, the over-voltage condition on at least the first I/O transistor, wherein the first I/O transistor comprises a P-channel PET, and the first over-voltage protection circuit comprises a first over-voltage protection transistor and a second over-voltage protection transistor, wherein the first and second over-voltage protection transistors comprise P-channel field effect transistors (FETs), and f) preventing, by the second over-voltage protection circuit, the over-voltage condition on at least the second I/O transistor, wherein the second I/O transistor comprises an N-channel FET, and the second over-voltage protection circuit comprises (i) a third over-voltage protection transistor and (ii) a fourth over-voltage protection transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs, wherein the over-voltage condition comprises at least one of a DC and a transient over-voltage condition, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms. - View Dependent Claims (2)
- I/O”
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3. An apparatus for protection from an over-voltage condition in an input/output (“
- I/O”
) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is couple to a second over-voltage protection circuit, comprising;a) a first bias voltage and a second bias voltage; b) a first dynamic bias circuit to generate a third bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer, wherein the first dynamic bias circuit comprises a first and a second N-channel field effect transistor (FET); c) a second dynamic bias circuit to generate a fourth bias voltage from either i) the second bias voltage, or ii) an output signal voltage of the buffer, wherein the second dynamic bias circuit comprises a first and a second P-channel FET; d) a first over-voltage protection circuit driven by the third bias voltage, wherein the first over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the first I/O transistor and wherein the first over-voltage protection circuit comprises (i) a first over-voltage protection transistor and (ii) a second over-voltage protection transistor, wherein the first and second over-voltage protection transistors comprise P-channel FETs; and e) a second over-voltage protection circuit driven by the fourth bias voltage, wherein the second over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the second I/O transistor and wherein the second over-voltage protection circuit comprises (i) a third over-voltage protection transistor and (ii) a fourth over-voltage protection transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs; wherein the first I/O transistor comprises a P-channel FET and the second I/O transistor comprises an N-channel FET, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11)
- I/O”
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12. An apparatus for protection from an over-voltage condition in an input/output (“
- I/O”
) buffer having first and second I/O transistors, wherein the first I/O transistor is coupled to a first over-voltage protection circuit, and the second I/O transistor is couple to a second over-voltage protection circuit, comprising;a) a first bias voltage; b) a first dynamic bias circuit configured to generate a second bias voltage from either i) the first bias voltage, or ii) an output signal voltage of the buffer, wherein the first dynamic bias circuit comprises a first and a second N-channel field effect transistor (FET); c) a second dynamic bias circuit configured to generate a third bias voltage from either i) the first bias voltage, or ii) the output signal voltage of the buffer, wherein the second dynamic bias circuit comprises a first and a second P-channel FET; d) a first over-voltage protection circuit further comprising a first over-voltage protection transistor driven by the first bias voltage and a second over-voltage protection transistor driven by the second bias voltage, wherein the first over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the first I/O transistor, wherein the first and second over-voltage protection transistors comprise P-channel FETs; and e) a second over-voltage protection circuit further comprising a third over-voltage protection transistor driven by the first bias voltage and a fourth over-voltage protection transistor driven by the third bias voltage, wherein the second over-voltage protection circuit is adapted to prevent DC and transient over-voltage conditions on the second I/O transistor, wherein the third and fourth over-voltage protection transistors comprise N-channel FETs, wherein the first I/O transistor comprises a P-channel FET and the second I/O transistor comprises an N-channel FET, and wherein the FETs are fabricated with a gate oxide thickness of substantially 26 Angstroms. - View Dependent Claims (13, 14)
- I/O”
Specification