Use of data latches in cache operations of non-volatile memories

• US 7,936,602 B2
• Filed: 06/30/2009
• Issued: 05/03/2011
• Est. Priority Date: 04/01/2005
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Li, Yan, Yero, Emilio
• Primary Examiner(s): Hoang; Huan
• Application Number:
  US12/495,200
• Publication Number:
  US 20090262578A1
• Time in Patent Office: 672 Days
• Field of Search: 365/185.03, 365/185.17, 365/185.22
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

Claims

1. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuits having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:

loading a first data set into a first plurality of the data latches;

performing a first operation on a first group of memory cells using all of the latches of the first plurality of the sets of data latches;

during said first operation, releasing some, but less than all, of the latches of the first plurality of the sets of data latches; and

during said first operation, caching a second data set for a second operation in the released ones of said first plurality of the sets of data latches.

2. The method of claim 1, wherein said second data set is supplied from external to the memory device.

3. The method of claim 1, wherein the first operation includes multiple phases and said second data set is read from a second group of memory cells distinct from the first group of memory cells, the second data set being read between phases of the first operation.

4. The method of claim 3, wherein the first operation is a write operation having alternating program and verify phases and the first set of data is the data to be written into the first group of memory cells.

5. The method of claim 4, wherein the cached data set is subsequently transferred out of said first plurality of the sets of data latches during the write operation.

6. The method of claim 4, wherein the alternating program and verify phases resume where write process was paused while the second data set was read.

7. The method of claim 4, wherein said memory cells are multi-level memory cells storing N bits of data, where N is greater than one, and wherein each of said sets of data latches includes N data latches and said first data set is N bit data.

8. The method of claim 3, wherein the first and second data sets correspond to distinct first and second word lines of the memory.

9. The method of claim 1, wherein each of said sets of latches is associated with a distinct bit line of the memory.

10. A method of operating a non-volatile memory device which includes an array of memory cells and a set of read/write circuits for operating on a group of memory cells of said array in parallel, each read/write circuits having a set of data latches for latching input and/or output data of a corresponding one of said group of memory cells, the method comprising:

storing a first set of data for a first group of the memory cells into the corresponding sets of data latches;

writing the first set of data into said first group of memory cells using all of the corresponding sets of data latches, wherein the writing includes alternating program and verify phases;

during the writing of the first set of data, releasing some, but less than all, of the corresponding sets of data latches

pausing said writing between one of the program phases and one of the verify phases;

subsequent to said pausing, reading a second set of data from a second group of the memory cells into the released latches of said corresponding sets of data latches; and

subsequent to said reading, resuming the paused writing.

11. The method of claim 10, wherein the writing is managed by a state machine, said pausing is in response to receiving a command for said reading, and the resuming is in response to completing the reading.

12. The method of claim 10, further comprising:

subsequent to said reading, transferred the second set of data out of the memory during the resumed writing.