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Semiconductor memory device

  • US 7,936,613 B2
  • Filed: 09/15/2008
  • Issued: 05/03/2011
  • Est. Priority Date: 09/17/2007
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device, comprising:

  • a plurality of banks;

    a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks; and

    a plurality of discharge drivers respectively assigned to the banks, and configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector.

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