Semiconductor memory device

• US 7,936,613 B2
• Filed: 09/15/2008
• Issued: 05/03/2011
• Est. Priority Date: 09/17/2007
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kang, Khil-Ohk
• Primary Examiner(s): Luu; Pho M
• Application Number:
  US12/210,927
• Publication Number:
  US 20090185432A1
• Time in Patent Office: 960 Days
• Field of Search: 365/189.07, 365/189.08, 365/230.03
• US Class Current: 365/189.07
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks, and a discharge drivers assigned to the respective banks. The discharge drivers are configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector.

Claims

1. A semiconductor memory device, comprising:

a plurality of banks;

a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks; and

a plurality of discharge drivers respectively assigned to the banks, and configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector.

2. The semiconductor memory device as recited in claim 1, further comprising:

a plurality of charge level detectors respectively assigned to the banks, and configured to detect a voltage level of the internal voltage terminals on the basis of a second target level in response to the respective active signals; and

a plurality of charge drivers respectively assigned to the banks, and configured to drive the internal voltage terminals to be charged in response to the respective active signals and respective charge control signals outputted from the plurality of charge level detectors.

3. The semiconductor memory device as recited in claim 1, wherein the common discharge level detector includes:

a voltage divider configured to divide the voltage level of the internal voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the first target level in response to an enable signal inputted as a bias; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the active signals.

4. The semiconductor memory device as recited in claim 3, wherein the voltage divider includes first and second resistors connected in series between the internal voltage terminals and a ground voltage terminal, and outputs the division voltage through a connection node between the first and second resistors.

5. The semiconductor memory device as recited in claim 3, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage;

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

6. The semiconductor memory device as recited in claim 3, wherein the enable signal logic determiner includes:

a NOR gate configured to perform a NOR operation on the active signals; and

an inverter configured to receive an output signal of the NOR gate to output the enable signal.

7. The semiconductor memory device as recited in claim 1, wherein each of the discharge drivers includes:

a selector configured to selectively apply the discharge control signal inputted via an input terminal to an output terminal in response to the active signal; and

a driver configured to drive the internal voltage terminal to be discharged with a variable driving force in response to the applied discharge control signal selectively outputted through the output terminal.

8. The semiconductor memory device as recited in claim 7, wherein the selector includes:

an inverter configured to receive the active signal to output an active inversion signal; and

a pass gate configured to selectively apply the discharge control signal applied to the input terminal to the output terminal in response to the active signal and the active inversion signal.

9. The semiconductor memory device as recited in claim 8, wherein the driver includes an NMOS transistor having a gate receiving an output signal of the pass gate, a drain connected to the internal voltage terminal, and a source connected to a ground voltage terminal.

10. A semiconductor memory device, comprising:

a plurality of banks, each including a bit line sense amplifier configured to sense and amplify data carried on a bit line, and power line driver configured to drive a power line of the bit line sense amplifier with an overdriving voltage or a core voltage inputted through core voltage terminals;

an overdriving pulse generator configured to generate a plurality of overdriving pulses for controlling overdriving operation of each of the banks in response to active signals corresponding to each of the banks;

a common discharge level detector configured to detect a voltage level of the core voltage terminals on the basis of a first target level in response to the overdriving pulses corresponding to the respective banks; and

a plurality of discharge drivers respectively assigned to the banks, and configured to drive the core voltage terminals to be discharged in response to the respective overdriving pulses and respective discharge control signals outputted from the common discharge level detector.

11. The semiconductor memory device as recited in claim 10, further comprising:

a plurality of charge level detectors respectively assigned to the banks, and configured to detect a voltage level of the core voltage terminals on the basis of a second target level in response to the respective active signals; and

a plurality of charge drivers respectively assigned to the banks, and configured to drive the core voltage terminals to be charged in response to the respective active signals and respective charge control signals outputted from the plurality of charge level detectors.

12. The semiconductor memory device as recited in claim 10, wherein the common discharge level detector includes:

a voltage divider configured to divide the voltage level of the core voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the first target level in response to an enable signal inputted as a bias;

a pulse delay configured to delay the overdriving pulses by predetermined delay times to generate a plurality of delay pulses; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the delay pulses.

13. The semiconductor memory device as recited in claim 12, wherein the voltage divider includes first and second resistors connected in series between the core voltage terminals and a ground voltage terminal, and outputs the division voltage through a connection node between the first and second resistors.

14. The semiconductor memory device as recited in claim 12, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage;

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

15. The semiconductor memory device as recited in claim 12, wherein the enable signal logic determiner includes:

a NOR gate configured to perform a NOR operation on the delay pulses; and

an inverter configured to receive an output signal of the NOR gate to output the enable signal.

16. The semiconductor memory device as recited in claim 12, wherein each of the discharge drivers includes:

a selector configured to selectively apply the discharge control signal inputted via an input terminal to an output terminal in response to the delay pulse; and

a driver configured to drive the core voltage terminal to be discharged with a variable driving force in response to the applied discharge control signal selectively outputted through the output terminal.

17. The semiconductor memory device as recited in claim 16, wherein the selector includes:

an inverter configured to receive the delay pulse to output an delay inversion pulse; and

a pass gate configured to selectively apply the discharge control signal applied to the input terminal to the output terminal in response to the delay pulse and the delay inversion pulse.

18. The semiconductor memory device as recited in claim 17, wherein the driver includes an NMOS transistor having a gate receiving an output signal of the pass gate, a drain connected to the core voltage terminal, and a source connected to a ground voltage terminal.

19. A semiconductor memory device, comprising:

a plurality of banks;

a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks;

a common charge level detector configured to detect a voltage level of the internal voltage terminals on the basis of a second target level in response to the active signals;

a plurality of discharge drivers respectively assigned to the banks, and configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector; and

a plurality of charge drivers respectively assigned to the banks, and configured to drive the internal voltage terminals to be charged in response to the respective active signals and respective charge control signals outputted from the common charge level detector.

20. The semiconductor memory device as recited in claim 19, wherein the common discharge level detector includes:

a voltage divider configured to divide the voltage level of the internal voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the first target level in response to an enable signal inputted as a bias; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the active signals.

21. The semiconductor memory device as recited in claim 20, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage,

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

22. The semiconductor memory device as recited in claim 19, wherein the common charge level detector includes:

a voltage divider configured to divide the voltage level of the internal voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the second target level in response to an enable signal inputted as a bias; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the active signals.

23. The semiconductor memory device as recited in claim 20, wherein the voltage divider includes first and second resistors connected in series between the internal voltage terminals and a ground voltage terminal, and outputs the division voltage through a connection node between the first and second resistors.

24. The semiconductor memory device as recited in claim 20, wherein the enable signal logic determiner includes

a NOR gate configured to perform a NOR operation on the active signals;

and

an inverter configured to receive an output signal of the NOR gate to output the enable signal.

25. The semiconductor memory device as recited in claim 22, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage;

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

26. The semiconductor memory device as recited in claim 19, wherein each of the discharge drivers includes:

a selector configured to selectively apply the discharge control signal inputted via an input terminal to an output terminal in response to the active signal; and

a driver configured to drive the internal voltage terminal to be discharged with a variable driving force in response to the applied discharge control signal selectively outputted through the output terminal.

27. The semiconductor memory device as recited in claim 26, wherein the selector includes:

an inverter configured to receive the active signal to output an active inversion signal; and

a pass gate configured to selectively apply the discharge control signal applied to the input terminal to the output terminal in response to the active signal and the active inversion signal.

28. The semiconductor memory device as recited in claim 27, wherein the driver includes an NMOS transistor having a gate receiving an output signal of the pass gate, a drain connected to the internal voltage terminal, and a source connected to a ground voltage terminal.

29. The semiconductor memory device as recited in claim 19, wherein each of the charge drivers includes:

a selector configured to selectively apply the charge control signal inputted via an input terminal to an output terminal in response to the active signal; and

a driver configured to drive the internal voltage terminal to be charged with a variable driving force in response to the applied charge control signal selectively outputted through the output terminal.

30. The semiconductor memory device as recited in claim 29, wherein the selector includes:

an inverter configured to receive the active signal to output an active inversion signal; and

a pass gate configured to selectively apply the charge control signal applied to the input terminal to the output terminal in response to the active signal and the active inversion signal.

31. The semiconductor memory device as recited in claim 30, wherein the driver includes a PMOS transistor having a gate receiving an output signal of the pass gate, a source connected to a power supply voltage terminal, and a drain connected to the internal voltage terminal.

32. A semiconductor memory device, comprising:

a plurality of banks, each including a bit line sense amplifier configured to sense and amplify data carried on a bit line, and a power line driver configured to drive a power line of the bit line sense amplifier with an overdriving voltage or a core voltage inputted through core voltage terminals;

an overdriving pulse generator configured to generate a plurality of overdriving pulses for controlling overdriving operation of each of the banks in response to active signals corresponding to each of the banks;

a common discharge level detector configured to detect a voltage level of the core voltage terminals on the basis of a first target level in response to the overdriving pulses corresponding to the respective banks;

a common charge level detector configured to detect a voltage level of the core voltage terminals on the basis of a second target level in response to the active signals;

a plurality of discharge drivers respectively assigned to the banks, and configured to drive the core voltage terminals to be discharged in response to the respective overdriving pulses and respective discharge control signals outputted from the common discharge level detector; and

a plurality of charge drivers respectively assigned to the banks, and configured to drive the core voltage terminals to be charged in response to the respective active signals and respective charge control signals outputted from the common charge level detector.

33. The semiconductor memory device as recited in claim 32, wherein the common discharge level detector includes:

a voltage divider configured to divide the voltage level of the core voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the first target level in response to an enable signal inputted as a bias;

a pulse delay configured to delay the overdriving pulses by predetermined delay times to generate a plurality of delay pulses; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the delay pulses.

34. The semiconductor memory device as recited in claim 33, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage;

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

35. The semiconductor memory device as recited in claim 33, wherein the voltage divider includes first and second resistors connected in series between the core voltage terminals and a ground voltage terminal, and outputs the division voltage through a connection node between the first and second resistors.

36. The semiconductor memory device as recited in claim 33, wherein the enable signal logic determiner includes:

a NOR gate configured to perform a NOR operation on the delay pulses; and

an inverter configured to receive an output signal of the NOR gate to output the enable signal.

37. The semiconductor memory device as recited in claim 32, wherein each of the discharge drivers includes:

a selector configured to selectively apply the discharge control signal inputted via an input terminal to an output terminal in response to the delay pulse; and

a driver configured to drive the core voltage terminal to be discharged with a variable driving force in response to the applied discharge control signal selectively outputted through the output terminal.

38. The semiconductor memory device as recited in claim 37, wherein the selector includes:

an inverter configured to receive the delay pulse to output an delay inversion pulse; and

a pass gate configured to selectively apply the discharge control signal applied to the input terminal to the output terminal in response to the delay pulse and the delay inversion pulse.

39. The semiconductor memory device as recited in claim 32, wherein the common charge level detector includes:

a voltage divider configured to divide the voltage level of the core voltage terminals by a predetermined ratio to generate a division voltage;

a voltage comparator configured to compare a level of the division voltage with a level of a reference voltage corresponding to the second target level in response to an enable signal inputted as a bias; and

an enable signal logic determiner configured to determine a logic level of the enable signal in response to the active signals.

40. The semiconductor memory device as recited in claim 39, wherein the voltage comparator includes:

a first NMOS transistor having a gate receiving the division voltage, a drain connected to a driving node and a source connected to a common node, and configured to control amount of current flowing between the driving node and the common node in response to a level of the division voltage;

a second NMOS transistor having a gate receiving the reference voltage, a drain connected to an output node and a source connected to the common node, and configured to control amount of current flowing between the output node and the common node in response to a level of the reference voltage;

first and second PMOS transistors connected to each other in a current mirror configuration between the driving node and the output node, and configured to control amount of current flowing through the driving node and the output node to be equal to each other; and

a third NMOS transistor having a gate receiving the enable signal, a drain connected to the common node and a source connected to a ground voltage terminal, and configured to be turned on in response to a logic level of the enable signal.

41. The semiconductor memory device as recited in claim 39, wherein the voltage divider includes first and second resistors connected in series between the core voltage terminals and a ground voltage terminal, and outputs the division voltage through a connection node between the first and second resistors.

42. The semiconductor memory device as recited in claim 39, wherein the enable signal logic determiner includes:

a NOR gate configured to perform a NOR operation on the active signals; and

an inverter configured to receive an output signal of the NOR gate to output the enable signal.

43. The semiconductor memory device as recited in claim 42, wherein the driver includes an NMOS transistor having a gate receiving an output signal of the pass gate, a drain connected to the core voltage terminal, and a source connected to a ground voltage terminal.

44. The semiconductor memory device as recited in claim 32, wherein each of the charge drivers includes:

a selector configured to selectively apply the charge control signal inputted via an input terminal to an output terminal in response to the active signal; and

a driver configured to drive the core voltage terminal to be charged with a variable driving force in response to the applied charge control signal selectively outputted through the output terminal.

45. The semiconductor memory device as recited in claim 44, wherein the selector includes:

an inverter configured to receive the active signal to output an active inversion signal; and

a pass gate configured to selectively apply the charge control signal applied to the input terminal to the output terminal in response to the active signal and the active inversion signal.

46. The semiconductor memory device as recited in claim 45, wherein the driver includes a PMOS transistor having a gate receiving an output signal of the pass gate, a source connected to a power supply voltage terminal, and a drain connected to the core voltage terminal.