Logical separation and accessing of descriptor memories

• US 7,936,758 B2
• Filed: 05/04/2010
• Issued: 05/03/2011
• Est. Priority Date: 03/22/2002
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Lim, Raymond Marcelino Manese, Libby, Jeffrey G.
• Primary Examiner(s): Jain; Raj K
• Application Number:
  US12/773,494
• Publication Number:
  US 20100215046A1
• Time in Patent Office: 364 Days
• Field of Search: None
• US Class Current: 370/392
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

Claims

1. A device comprising:

a plurality of data unit processing components, each of the plurality of data unit processing components, including;

a lower layer execution unit to;

receive header information, where the header information includes template data, tag descriptor data, and lower layer descriptor data, and

process the header information to obtain lower layer header data, the lower layer execution unit performing the processing of the received second header information in parallel with processing of the header information by a higher layer execution unit associated with the one of the plurality of data unit processing components.

2. The device of claim 1, where the header information further includes header data associated with a previously processed data unit.

3. The device of claim 1, further comprising:

a plurality of mailbox registers to;

store information to allow the lower layer execution unit to share data with the higher layer execution unit.

4. The device of claim 3, where at least one mailbox register, of the plurality of mailbox registers, accepts data from the lower layer execution unit and does not accept data from the higher layer execution unit.

5. The device of claim 3, where at least one mailbox register, of the plurality of mailbox registers, includes a validity bit that indicates whether the one mailbox register is ready to be written or read.

6. The device of claim 1, further comprising:

a build component to;

receive the lower layer header data from the lower layer execution unit, and

form a header based on the lower layer header data and higher layer header data received from the higher layer execution unit.

7. The device of claim 1, where data unit processing component, of the plurality of data unit processing components, loads information relating to a first header simultaneously with acquiring information relating to a second header.

8. The device of claim 1, where the lower layer execution unit includes a plurality of execution sections, including:

a first execution section, of the plurality of execution sections, to process the header information, and

a second execution section, of the plurality of execution sections, to compute a checksum.

9. The device of claim 1 further comprising:

a dispatch component to;

receive the header information associated with a data unit;

parse the received header information, and

to direct the parsed header information to two or more of the plurality of data unit processing components.

10. A device comprising:

a lower layer execution unit to;

receive header information, where the header information includes template data, tag descriptor data, and lower layer descriptor data, and

generate lower layer header data based on the header information, the lower layer execution unit performing the generating the lower layer header data in parallel with generation of higher layer header data, associated with the header information, by a higher layer execution unit.

11. The device of claim 10, further comprising:

a dispatch component to;

parse the header information to create parsed header information portions, and

direct one of the parsed header information portions to the lower layer execution unit.

12. The device of claim 10, further comprising:

at least one mailbox register to store information, the at least one mailbox register allowing the lower layer execution unit to share data with the higher layer execution unit.

13. The device of claim 12, where the at least one mailbox register includes a first mailbox register and a second mailbox register, where the first mailbox register cannot be written to by the higher layer execution unit, and where the second mailbox register cannot be written to by the lower layer execution unit.

14. The device of claim 12, where the at least one mailbox register includes a validity bit that indicates whether data associated with the at least one mailbox register is ready to be written or read.

15. The device of claim 10, further comprising:

a build component to combine the higher layer header data and the lower layer header data to form a header.

16. The device of claim 10, where the lower layer execution unit is further to compute a checksum for the received second header information.

17. A method implemented in a device comprising a plurality of data unit processing components, the method comprising:

receiving, at a lower layer execution unit in one of the a plurality of data unit processing components, header information including at least one of template data, tag descriptor data, or lower layer descriptor data;

generating, at the lower layer execution unit, lower layer header data based on the header information, where generating the lower layer header data occurring in parallel with generating, by one of the plurality of data unit processing components, higher layer header data associated with the header information; and

forming, based on the higher layer header data and the lower layer header data, a header.

18. The method of claim 17, further comprising:

transferring data to and from the lower layer execution unit using a second, different mailbox register.

19. The method of claim 17, further comprising,

computing a checksum for the header information, and

verifying the header information based on the checksum.