Method and system of cycle slip framing in a deserializer
First Claim
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1. A method of cycle slip framing comprising:
- receiving a slip bit signal associated with a serial bit data stream;
in response to receiving said slip bit signal, applying a single control signal to a multiplexor to delay an edge of a clock signal;
generating from the clock signal a plurality of divided clocks; and
applying the plurality of divided clocks to a deserializer to effect a bit slip in the deserializer and to move a character frame with respect to said serial bit data stream.
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Abstract
A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit slip that results in the moving of a character frame in the recovered data of a deserializer. According to one embodiment of the invention, the moving of the character frame is prompted by a single control signal of a clock divider circuit which causes the removal of a single clock cycle of a clock signal supplied to said deserializer.
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19 Claims
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1. A method of cycle slip framing comprising:
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receiving a slip bit signal associated with a serial bit data stream; in response to receiving said slip bit signal, applying a single control signal to a multiplexor to delay an edge of a clock signal; generating from the clock signal a plurality of divided clocks; and
applying the plurality of divided clocks to a deserializer to effect a bit slip in the deserializer and to move a character frame with respect to said serial bit data stream. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. In a digital system, a method comprising:
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a) receiving an incident clock signal and dividing said incident clock signal to produce a plurality of divided clock signals that are provided from a plurality of sequential circuits for respective stages of a deserializer; b) applying a control signal to a multiplexor to remove a clock cycle from at least one of said plurality of divided clock signals in response to receiving a slip bit signal; and c) resuming the dividing of said incident clock signal according to a) upon a next clock cycle following b), wherein removing said clock cycle causes said deserializer to skip a data received by the deserializer. - View Dependent Claims (9, 10, 11, 12)
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13. A receiver circuit comprising:
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a logic circuit for receiving a slip bit signal and for generating a synchronized slip bit signal in response thereto; and a clock divider circuit coupled with the logic circuit for; a) receiving an incident clock signal and dividing said incident clock signal to produce at least one output clock signal, wherein the at least one output clock signal is for a respective stage of a deserializer; b) removing a clock cycle from said at least one output clock signal in response to receiving said slip bit signal; and c) resuming the generation of said at least one output clock signal according to a) upon a next clock cycle following b) wherein removing said clock cycle causes said deserializer to skip a data bit that it receives from an incoming serial bit data stream; and said deserializer that provides deserialized data according to a character frame that is related to said incoming serial bit data stream and said at least one output clock signal. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification