Methods and apparatus for dynamically switching between polling and interrupt mode for a ring buffer of a network interface card

• US 7,937,499 B1
• Filed: 07/09/2004
• Issued: 05/03/2011
• Est. Priority Date: 07/09/2004
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Oracle America, Inc. (Oracle Corporation)
• Inventors: Tripathi, Sunay
• Primary Examiner(s): Dharia; Rupal D
• Assistant Examiner(s): MCADAMS, BRAD
• Application Number:
  US10/888,521
• Time in Patent Office: 2,489 Days
• Field of Search: 709/250, 709/232, 710/19, 710/48, 710/206, 710/261
• US Class Current: 709/250
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

Methods and apparatus for processing packets in a computer system including an operating system and a network interface card (NIC) are disclosed. The NIC having a plurality of ring buffers is configured to operate in either a polling mode or an interrupt mode for a particular ring buffer. When the NIC is in the polling mode for a ring buffer, the NIC is periodically polled to determine whether one or more packets have been received by the ring buffer. When the NIC is in the interrupt mode, the operating system is capable of receiving an interrupt indicating that the ring buffer of the NIC has received one or more packets. The operating system is capable of instructing the NIC to change its mode from the polling mode to the interrupt mode for a particular ring buffer, and from the interrupt mode to the polling mode for a particular ring buffer.

Claims

1. A method of configuring a network interface card, comprising:

mapping each one of a plurality of ring buffers associated with a network interface card (NIC) to one of a plurality of processors, wherein a first queue is associated with a first processor of the plurality of processors and a second queue is associated with a second processor of the plurality of processors, and, wherein the NIC comprises a driver to facilitate communication between the NIC and the plurality of processors;

wherein the NIC is dynamically instructed, by an operating system, to individually operate each of the plurality of ring buffers in one of a polling mode and an interrupt mode, wherein the operating system is configured to communicate with the NIC using at least one of a plurality of ring buffer identifiers and an application programming interface of the driver, wherein each of the plurality of ring buffers is associated with one of the plurality of ring buffer identifiers;

operating a first of the plurality of ring buffers associated with the NIC in the interrupt mode by;

obtaining, from the mapping, a first ring buffer identifier of the plurality of ring buffer identifiers associated with the first processor of the plurality of processors, and

sending an instruction comprising the first ring buffer identifier to the NIC,

wherein the first ring buffer is operated in the interrupt mode when the memory mapped to the one of the plurality of ring buffers has less than a predefined number of packets or packets are received from the one of the plurality of ring buffers at less than a predefined rate;

operating a second of the plurality of ring buffers associated with the NIC in a polling mode by;

obtaining, from the mapping, a second ring buffer identifier of the plurality of ring buffer identifiers associated with the second processor of the plurality of processors, and

sending an instruction comprising the second ring buffer identifier to the NIC,

wherein the second ring buffer is operated in the polling mode when the memory mapped to the one of the plurality of ring buffers has greater than a predefined number of packets or packets are received from one of the plurality of ring buffers at greater than a predefined rate;

transferring, by the operating system, packets from the first ring buffer to the first queue of the first processor; and

transferring, by the operating system, packets from the second ring buffer to the second queue of the second processor.

2. The method as recited in claim 1, wherein operating one of the plurality of ring buffers associated with the NIC in the interrupt mode comprises:

enabling the NIC to interrupt one of the plurality of processors when a packet is received by one of the plurality of ring buffers mapped thereto.

3. The method as recited in claim 1, wherein operating one of the plurality of ring buffers associated with the NIC in a polling mode comprises:

disabling the NIC from interrupting one of the plurality of processors when a packet is received by one of the plurality of ring buffers mapped thereto.

4. A method of processing packets in a computer system including an operating system and a network interface card (NIC), the NIC having a plurality of ring buffers, comprising:

mapping each one of the plurality of ring buffers associated with the NIC to one of a plurality of processors, wherein a first queue is associated with one a first processor of the plurality of processors and a second queue is associated with a second processor of the plurality of processors, wherein the NIC comprises a driver to facilitate communication between the NIC and the plurality of processors;

polling the NIC to determine whether one or more packets have been received by a first ring buffer of the plurality of ring buffers when the NIC is in a polling mode for the first ring buffer;

receiving an interrupt from the NIC when the NIC is in an interrupt mode for a second ring buffer of the plurality of ring buffers, the interrupt indicating that the second ring buffer of the NIC has received one or more packets,

wherein the NIC is capable of being dynamically instructed, by the operating system, to individually operate each of the plurality of ring buffers in one of the polling mode and the interrupt mode, wherein the operating system is configured to communicate with the NIC using at least one of a plurality of ring buffer identifiers and an application programming interface of the driver, wherein each of the plurality of ring buffers is associated with one of the plurality of ring buffer identifiers;

obtaining a first ring buffer identifier of the plurality of ring buffer identifiers corresponding to the first ring buffer and a second ring buffer identifier of the plurality of ring buffer identifiers corresponding to the second ring buffer;

transferring, by the operating system, packets from the first ring buffer to the first queue of the first processor associated with the first ring buffer identifier obtained from the mapping; and

transferring, by the operating system, packets from the second ring buffer to the second queue of the second processor associated with the second ring buffer identifier obtained from the mapping, when the interrupt occurs.

5. The method as recited in claim 4, wherein the interrupt identifies the second ring buffer.

6. The method as recited in claim 4, wherein the mapping is provided in an IP layer of the kernel of the operating system.

7. The method as recited in claim 4, wherein each one of the plurality of processors mapped to one of the plurality of ring buffers is responsible for performing polling and receiving an interrupt from the one of the plurality of ring buffers.

8. The method as recited in claim 4, further comprising:

obtaining packets from the first ring buffer of the NIC and processing the packets obtained from the one of the plurality of ring buffers of the NIC.

9. The method as recited in claim 4, further comprising:

instructing the NIC to operate in the polling mode for the first ring buffer when packets are being received frequently from the first ring buffer of the NIC; and

instructing the NIC to operate in the interrupt mode for the second ring buffer when packets are being received infrequently from the second ring buffer of the NIC.

10. The method as recited in claim 4, further comprising:

instructing the NIC to operate in the polling mode for the first ring buffer when a number of packets received per second from the first ring buffer of the NIC is greater than a predefined number; and

instructing the NIC to operate in the interrupt mode for the second ring buffer when the number of packets received per second from the second ring buffer of the NIC is less than the predefined number.

11. The method as recited in claim 4, wherein the computer system includes a plurality of processors, each of the plurality of processors having an associated memory, each of the plurality of ring buffers being mapped to one of the plurality of processors and its associated memory, the method further comprising:

instructing the NIC to operate in the polling mode for the first ring buffer when the memory mapped to first ring buffer includes greater than a predefined number of packets.

12. The method as recited in claim 11, further comprising:

instructing the NIC to operate in the interrupt mode for the second ring buffer when the memory mapped to the second ring buffer includes less than the predefined number of packets.

13. The method as recited in claim 4, further comprising:

ascertaining whether the NIC is in the interrupt mode or the polling mode for one or more of the plurality of ring buffers.

14. The method as recited in claim 4, further comprising:

initializing the NIC such that the NIC is in the interrupt mode for one or more of the plurality of ring buffers.

15. The method as recited in claim 4, further comprising:

instructing the NIC to switch from the polling mode to the interrupt mode for one or more of the plurality of ring buffers.

16. The method as recited in claim 15, wherein instructing the NIC to switch from the polling mode to the interrupt mode comprises instructing the NIC to switch from the polling mode to the interrupt mode for a specified period of time.

17. The method as recited in claim 4, further comprising:

instructing the NIC to switch from the interrupt mode to the polling mode for one or more of the plurality of ring buffers.

18. The method as recited in claim 17, wherein instructing the NIC to switch from the interrupt mode to the polling mode comprises instructing the NIC to switch from the interrupt mode to the polling mode for a specified period of time.

19. The method as recited in claim 4, wherein the packets are transferred simultaneously from the first ring buffer to the first processor and the second ring buffer to the second processor.

20. The method as recited in claim 4, further comprising:

instructing the NIC to switch from the polling mode to the interrupt mode for the first ring buffer when no packets are in the first queue associated with one selected from a group consisting of the first processor or the first ring buffer of the NIC.

21. The method as recited in claim 4, further comprising:

instructing the NIC to switch from the interrupt mode to the polling mode for the second ring buffer when the interrupt is received from the NIC.

22. The method as recited in claim 4, further comprising:

processing each of the packets in the first queue of the first processor and the second queue of the second processor.

23. The method as recited in claim 22, wherein each of the packets in the first and second queues corresponds to one or more network connections.

24. The method as recited in claim 22, further comprising:

instructing the NIC to switch from the interrupt mode to the polling mode for the second ring buffer prior to processing each of the packets in the second queue of the second processor.

25. The method as recited in claim 22, further comprising:

instructing the NIC to switch from the interrupt mode to the polling mode for the second ring buffer.

26. The method as recited in claim 25, further comprising:

after processing each of the packets in the second queue, polling the second ring buffer of the NIC to determine if one or more packets have been received by the second ring buffer of the NIC; and

if one or more packets have been received by the second ring buffer of the NIC, transferring the one or more packets from the second ring buffer to the second queue associated with the second processor and processing each of the packets in the second queue.

27. The method as recited in claim 26, further comprising:

if no more packets have been received by the second ring buffer of the NIC, instructing the NIC to switch from the polling mode to the interrupt mode for the second ring buffer.

28. The method as recited in claim 25, further comprising:

instructing the NIC to switch from the polling mode to the interrupt mode for the second ring buffer after processing each of the packets in the second queue of the second processor.

29. The method as recited in claim 22, further comprising:

instructing the NIC to switch from the polling mode to the interrupt mode for the first ring buffer after processing each of the packets in the first queue of the first processor.

30. The method as recited in claim 4, further comprising:

instantiating a worker thread for processing packets in the first and second queues.

31. The method as recited in claim 30, wherein the worker thread or a second worker thread is responsible for transferring packets from the first and second ring buffers to the first and second queues.

32. The method as recited in claim 30, wherein the worker thread is responsible for instructing the NIC to switch from polling mode to interrupt mode for the first ring buffer when no packets are in the first queue associated with the first processor or the first ring buffer.

33. The method as recited in claim 30, wherein the worker thread is responsible for instructing the NIC to switch from the interrupt mode to the polling mode for the second ring buffer after an interrupt identifying the second ring buffer is received from the NIC.

34. The method as recited in claim 4, further comprising:

instructing the NIC to enter the polling mode for the first ring buffer identified by a corresponding ring buffer identifier.

35. The method as recited in claim 4, further comprising:

instructing the NIC to enter the interrupt mode for the second ring buffer identified by a corresponding ring buffer identifier.

36. The method as recited in claim 35, wherein the interrupt includes the corresponding ring buffer identifier.

37. The method as recited in claim 4, further comprising:

instructing the NIC to operate in the polling mode for the first ring buffer when a packet that is received from the first ring buffer or transmitted via the first ring buffer is already being processed and one or more packets are queued in the first queue associated with the first processor; and

instructing the NIC to operate in the interrupt mode for the first ring buffer when there are no queued packets in the first queue associated with the first processor.

38. A computer system, comprising:

a plurality of processors;

an operating system;

a network interface card (NIC) coupled to the operating system and having a first ring buffer and a second ring buffer, wherein each of the first and second ring buffers is associated with one of a plurality of ring buffer identifiers;

a mapping stored in the computer system configured to map each ring buffers to one of the plurality of processors and a corresponding queue,

wherein a first queue is associated with a first processor of the plurality of processors and a second queue is associated with a second processor of the plurality of processors

wherein the NIC is capable of being dynamically instructed, by the operating system, to individually operate the first ring buffer in an interrupt mode and the second ring buffer in a polling mode,

wherein the operating system is configured to;

obtain, from the mapping, a first ring buffer identifier of the plurality of ring buffer identifiers associated with a first processor of the plurality of processors;

send an instruction comprising the first ring buffer identifier to the NIC to operate the first ring buffer in the interrupt mode when the first ring buffer has less than a predefined number of packets or packets are received from the first ring buffer at less than a predefined rate;

obtain, from the mapping, a second ring buffer identifier of the plurality of ring buffer identifiers associated with a second processor of the plurality of processors;

send an instruction comprising the second ring buffer identifier to the NIC to operate the second ring buffer in the polling mode when the second ring buffer has greater than the predefined number of packets or packets are received from the second ring buffer at more than the predefined rate;

transfer packets from the first ring buffer to the first queue corresponding to the first processor associated with the first ring buffer identifier in the mapping; and

transfer packets from the second ring buffer to the second queue corresponding to the second processor associated with the second ring buffer identifier in the mapping.

39. The computer system as recited in claim 38, the NIC being unable to interrupt the operating system on behalf of one of the plurality of ring buffers when in the polling mode for the one of the plurality of ring buffers for packets having low priority and being able to interrupt the system on behalf of the one of the plurality of ring buffers when in the polling mode for the one of the plurality of ring buffers for packets having high priority.

40. The computer system as recited in claim 38, wherein the first and second queues are adapted for storing inbound and outbound packets.

41. The computer system as recited in claim 38, further comprising:

the operating system for instructing the NIC to switch from the interrupt mode to the polling mode for one or more of the plurality of ring buffers; and

the operating system for instructing the NIC to switch from the polling mode to the interrupt mode for one or more of the plurality of ring buffers.

42. The computer system as recited in claim 38, further comprising:

a driver including a call interface between a kernel of the operating system and the NIC, the call interface enabling the kernel of the operating system to instruct the NIC to enter the interrupt mode or the polling mode for one or more of the plurality of ring buffers.