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Managing cache coherency in a data processing apparatus

  • US 7,937,535 B2
  • Filed: 02/22/2007
  • Issued: 05/03/2011
  • Est. Priority Date: 02/22/2007
  • Status: Expired due to Fees
First Claim
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1. A data processing apparatus, comprising:

  • a plurality of processing units configured to perform data processing operations requiringaccess to data in shared memory, each processing unit when access to data is required issuing an access request specifying an address in memory associated with that data;

    each processing unit having a cache associated therewith configured to store a subset of said data for access by that processing unit, said cache comprising a plurality of data arrays and a corresponding plurality of TAG arrays, each data array including a plurality of cache lines configured to store data values, and the corresponding TAG array having a plurality of TAG entries, where each TAG entry stores a TAG value that is associated with the data values in a corresponding cache line, the cache being arranged as a plurality of segments, where each segment comprises a plurality of said cache lines, each cache being responsive to at least a subset of the access requests issued by its associated processing unit to perform a lookup procedure involving access to at least one TAG array of the cache;

    each cache having indication circuitry associated therewith containing segment filtering data, the indication circuitry being separate from the TAG arrays of the cache and being responsive to an address portion of the address to reference the segment filtering data to provide, for each of at least a subset of the segments, an indication as to whether the data associated with that address is either definitely not stored in that segment or is potentially stored within that segment, the indications produced by the indication circuitry being used by the cache to affect the lookup procedure; and

    cache coherency circuitry employing a cache coherency protocol configured to ensure that said data accessed by each processing unit is up-to-date, the cache coherency circuitry having snoop indication circuitry associated therewith whose content is derived from the segment filtering data of each said indication circuitry, for certain access requests the cache coherency circuitry initiating a coherency operation during which the snoop indication circuitry is referenced to determine whether any of said caches require subjecting to a snoop operation, for each cache for which it is determined a snoop operation should be performed, the cache coherency circuitry being arranged to issue a notification to that cache identifying the snoop operation to be performed;

    wherein each said notification issued by the cache coherency circuitry identifies which segments of the cache are to be subjected to the snoop operation.

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