Managing cache coherency in a data processing apparatus

• US 7,937,535 B2
• Filed: 02/22/2007
• Issued: 05/03/2011
• Est. Priority Date: 02/22/2007
• Status: Expired due to Fees

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Ford, Simon Andrew, Biles, Stuart David, Özer, Emre
• Primary Examiner(s): RIGOL, YAIMA
• Application Number:
  US11/709,279
• Publication Number:
  US 20080209133A1
• Time in Patent Office: 1,531 Days
• Field of Search: 711141-146
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filtering data to indicate whether the data is either definitely not stored or is potentially stored in that segment. Cache coherency circuitry ensures that data accessed by each processing unit is up-to-date and has snoop indication circuitry whose content is derived from the already-provided segment filtering data. For certain access requests, the cache coherency circuitry initiates a coherency operation during which the snoop indication circuitry determines whether any of the caches requires a snoop operation. For each cache that does, the cache coherency circuitry issues a notification to that cache identifying the snoop operation to be performed.

Claims

1. A data processing apparatus, comprising:

a plurality of processing units configured to perform data processing operations requiring

access to data in shared memory, each processing unit when access to data is required issuing an access request specifying an address in memory associated with that data;

each processing unit having a cache associated therewith configured to store a subset of said data for access by that processing unit, said cache comprising a plurality of data arrays and a corresponding plurality of TAG arrays, each data array including a plurality of cache lines configured to store data values, and the corresponding TAG array having a plurality of TAG entries, where each TAG entry stores a TAG value that is associated with the data values in a corresponding cache line, the cache being arranged as a plurality of segments, where each segment comprises a plurality of said cache lines, each cache being responsive to at least a subset of the access requests issued by its associated processing unit to perform a lookup procedure involving access to at least one TAG array of the cache;

each cache having indication circuitry associated therewith containing segment filtering data, the indication circuitry being separate from the TAG arrays of the cache and being responsive to an address portion of the address to reference the segment filtering data to provide, for each of at least a subset of the segments, an indication as to whether the data associated with that address is either definitely not stored in that segment or is potentially stored within that segment, the indications produced by the indication circuitry being used by the cache to affect the lookup procedure; and

cache coherency circuitry employing a cache coherency protocol configured to ensure that said data accessed by each processing unit is up-to-date, the cache coherency circuitry having snoop indication circuitry associated therewith whose content is derived from the segment filtering data of each said indication circuitry, for certain access requests the cache coherency circuitry initiating a coherency operation during which the snoop indication circuitry is referenced to determine whether any of said caches require subjecting to a snoop operation, for each cache for which it is determined a snoop operation should be performed, the cache coherency circuitry being arranged to issue a notification to that cache identifying the snoop operation to be performed;

wherein each said notification issued by the cache coherency circuitry identifies which segments of the cache are to be subjected to the snoop operation.

2. A data processing apparatus as claimed in claim 1, wherein the snoop indication circuitry maintains a copy of at least part of the segment filtering data of each said indication circuitry.

3. A data processing apparatus as claimed in claim 1, wherein the snoop indication circuitry maintains summary data derived from the segment filtering data of each said indication circuitry.

4. A data processing apparatus as claimed in claim 1, wherein said at least a subset of the segments comprises all segments.

5. A data processing apparatus as claimed in claim 1, wherein at least one cache is a set associative cache, and for that at least one cache each segment comprises at least part of a way of the cache.

6. A data processing apparatus as claimed in claim 5, wherein each segment comprises a way of the cache.

7. A data processing apparatus as claimed in claim 1, wherein at least one cache is a set associative cache, and for that at least one cache each segment comprises at least part of a set of the cache.

8. A data processing apparatus as claimed in claim 1, wherein at least one indication circuitry comprises:

guardian storage for storing said segment filtering data in the form of guarding data; and

hash circuitry for performing a hash operation on the address portion in order to reference the guarding data to determine each said indication.

9. A data processing apparatus as claimed in claim 8, wherein for each segment the guardian storage comprises:

counter circuitry having a plurality of counter entries, each counter entry containing a count value; and

vector circuitry having a vector entry for each counter entry in the counter circuitry, each vector entry containing a value which is set when the count value in the corresponding counter entry changes from a zero value to a non-zero value, and which is cleared when the count value in the corresponding counter entry changes from a non-zero value to a zero value.

10. A data processing apparatus as claimed in claim 9, wherein the snoop indication circuitry maintains a copy of the vector entries provided by each of said at least one indication circuitry.

11. A data processing apparatus as claimed in claim 9, wherein the snoop indication circuitry maintains summary data derived from the vector entries provided by each of said at least one indication circuitry.

12. A data processing apparatus as claimed in claim 11, wherein for each segment the vector entries in the corresponding vector circuitry are partitioned to form a plurality of groups and the summary data is derived for each group.

13. A data processing apparatus as claimed in claim 12, wherein the hash operation performed by the hash circuitry is arranged such that each group contains vector entries pertaining to consecutive cache blocks in a memory region, such that the summary data enables the cache coherency circuitry to determine on a memory region by memory region basis whether a snoop operation needs to be performed in respect of the associated segment.

14. A data processing apparatus as claimed in claim 1, wherein at least one cache is a set associative cache, for that at least one cache each segment comprises a way of the cache, and the associated indication circuitry comprises:

a partial tag store for storing said segment filtering data in the form of partial tag values, for each set a partial tag value being provided for each way of that set;

the associated indication circuitry being arranged to identify from the address the set being accessed and to determine for each way, by comparing one or more tag bits of the address with the relevant partial tag value, whether the data is either definitely not stored in that way or is potentially stored within that way.

15. A data processing apparatus as claimed in claim 14, wherein the snoop indication circuitry maintains a copy of the partial tag values.

16. A data processing apparatus as claimed in claim 14, wherein the snoop indication circuitry maintains summary data derived from the partial tag values.

17. A data processing apparatus as claimed in claim 1, wherein the cache coherency circuitry includes a snoop control unit and a plurality of coherency control units, each coherency control unit being associated with one of the processing units and its associated cache, and being arranged to determine which of the access requests issued by the associated processing unit should cause a coherency operation to be initiated by the snoop control unit.

18. A method of managing cache coherency in a data processing apparatus, the data processing apparatus comprising a plurality of processing units performing data processing operations requiring access to data in shared memory, each processing unit when access to data is required issuing an access request specifying an address in memory associated with that data, each processing unit having a cache associated therewith storing a subset of said data for access by that processing unit, said cache comprising a plurality of data arrays and a corresponding plurality of TAG arrays, each data array including a plurality of cache lines storing data values, and the corresponding TAG array having a plurality of TAG entries, where each TAG entry stores a TAG value that is associated with the data values in a corresponding cache line, the cache being arranged as a plurality of segments, where each segment comprises a plurality of said cache lines, each cache being responsive to at least a subset of the access requests issued by its associated processing unit to perform a lookup procedure involving access to at least one TAG array of the cache, each cache having indication circuitry associated therewith containing segment filtering data, the indication circuitry being separate from the TAG arrays of the cache and being responsive to an address portion of the address to reference the segment filtering data to provide, for each of at least a subset of the segments, an indication as to whether the data associated with that address is either definitely not stored in that segment or is potentially stored within that segment, the indications produced by the indication circuitry being used by the cache to affect the lookup procedure, the method comprising the steps of:

providing cache coherency circuitry employing a cache coherency protocol configured to ensure data accessed by each processing unit is up-to-date;

providing snoop indication circuitry associated with the cache coherency circuitry;

deriving the content of the snoop indication circuitry from the segment filtering data of each said indication circuitry;

for certain access requests, initiating a coherency operation during which the snoop indication circuitry is referenced to determine whether any of said caches require subjecting to a snoop operation; and

for each cache for which it is determined a snoop operation should be performed, issuing a notification to that cache identifying the snoop operation to be performed,

wherein each said notification identifies which segments of the cache are to be subjected to the snoop operation.

19. A data processing apparatus, comprising:

a plurality of processing means for performing data processing operations requiring access to data in shared memory means, each processing means for issuing, when access to data is required, an access request specifying an address in memory associated with that data;

each processing means having a cache means associated therewith for storing a subset of said data for access by that processing means, said cache means comprising a plurality of data array means and a corresponding plurality of TAG array means, each data array means including a plurality of cache lines for storing data values, and the corresponding TAG array means having a plurality of TAG entries, where each TAG entry stores a TAG value that is associated with the data values in a corresponding cache line, the cache means being arranged as a plurality of segments, where each segment comprises a plurality of said cache lines, each cache means for performing a lookup procedure in response to at least a subset of the access requests issued by its associated processing means, the lookup procedure involving access to at least one TAG array means of the cache means;

each cache means having indication means associated therewith containing segment filtering data, the indication means being separate from the TAG arrays of the cache and for referencing, in response to an address portion of the address, the segment filtering data to provide, for each of at least a subset of the segments, an indication as to whether the data associated with that address is either definitely not stored in that segment or is potentially stored within that segment, the indications produced by the indication means being used by the cache means to affect which TAG arrays of the cache are accessed during the lookup procedure; and

cache coherency means for employing a cache coherency protocol to ensure that said data accessed by each processing means is up-to-date, the cache coherency means having snoop indication means associated therewith whose content is derived from the segment filtering data of each said indication means, for certain access requests the cache coherency means initiating a coherency operation during which the snoop indication means is referenced to determine whether any of said cache means require subjecting to a snoop operation, for each cache means for which it is determined a snoop operation should be performed, the cache coherency means issuing a notification to that cache means identifying the snoop operation to be performed,

wherein each said notification issued by the cache coherency means identifies which segments of the cache are to be subjected to the snoop operation.