External memory controller node
First Claim
Patent Images
1. A computing machine embodied in an integrated circuit comprising:
- a memory interface coupled to an external memory;
a plurality of heterogeneous computational nodes configured to make memory requests for accesses to the external memory; and
a memory controller to manage a sequence to allow accesses by the heterogeneous computational nodes to the external memory in response to the memory requests.
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Accused Products
Abstract
A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
401 Citations
46 Claims
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1. A computing machine embodied in an integrated circuit comprising:
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a memory interface coupled to an external memory; a plurality of heterogeneous computational nodes configured to make memory requests for accesses to the external memory; and a memory controller to manage a sequence to allow accesses by the heterogeneous computational nodes to the external memory in response to the memory requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A computing machine embodied in an integrated circuit, the computing machine in communication with an external memory device, the integrated circuit comprising:
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a plurality of heterogeneous computational nodes configured to make memory requests for accesses to the external memory device; a controller to manage a sequence to allow accesses by the heterogeneous computing nodes to the external memory device in response to the memory requests. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. An adaptive computing machine embodied in an integrated circuit, the adaptive computing machine comprising:
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a memory interface coupled to an external memory; a plurality of heterogeneous computational nodes configured to make memory requests for accesses to the external memory; a memory controller to manage a sequence to allow accesses by the heterogeneous computational nodes to the external memory in response to the memory requests; and a programmable interconnection network providing programmable interconnections among the heterogeneous computational nodes and the memory controller. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. An adaptive computing machine embodied in an integrated circuit and in communication with an external memory device, the adaptive computing machine comprising:
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a plurality of heterogeneous computational nodes configured to make memory requests for data transfer to the external memory device; a controller to manage a sequence to allow accesses by the heterogeneous computing nodes to the external memory device in response to the memory requests; and a programmable interconnection network to provide programmable interconnections among the heterogeneous computational nodes and the controller. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46)
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Specification