Error detection in physical interfaces for point-to-point communications between integrated circuits

• US 7,937,644 B2
• Filed: 02/24/2010
• Issued: 05/03/2011
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Schmidt, Brian K., Butcher, Lawrence Llewelyn
• Primary Examiner(s): Abraham; Esaw T
• Application Number:
  US12/712,124
• Publication Number:
  US 20100153805A1
• Time in Patent Office: 433 Days
• Field of Search: 714/758, 714/781, 714/799
• US Class Current: 714/758
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0092 Error control systems characterised by the topology of the transmission link
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“ICs”) includes an N-bit-to-N+2-bit (“N bit/(N+2) bit”) physical layer (“PHY”) encoder configured to insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and encode said N+1 unencoded data bits to yield N+2 encoded data bits. The apparatus further includes an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit, wherein N represents any integer number of data bits.

Claims

1. An apparatus for generating error-detection codes in a physical interface for the transmission of data communications between integrated circuits (“

ICs”

), the apparatus comprising;

an N bit/(N+2) bit physical layer (“

PHY”

) encoder configured to;

insert a physical interface error detection bit with N application data bits to form N+1 unencoded data bits, and

encode said N+1 unencoded data bits to yield N+2 encoded data bits; and

an error-detection code generator configured to generate a number of bits constituting an error-detection code that includes said physical interface error detection bit,

wherein N represents any integer number of data bits.

2. The apparatus of claim 1, further comprising a serializer configured to serialize said N+2 encoded data bits to form serial N+2 encoded data bits, thereby interleaving error-detection data bits with other data bits.

3. The apparatus of claim 1, further comprising storage to store a group of data bits that include said N application data bits, said error-detection code generator being configured to examine said group of data bits to generate said error-detection code.

4. The apparatus of claim 3, further comprising a transmitter error corrector configured to retransmit one or more subsets of said group of data bits when said transmitter error corrector receives a request for retransmission.

5. The apparatus of claim 1, wherein N is one of 8, 12, 18, 64 and 128.