Method for forming a substrate contact for advanced SOI devices based on a deep trench capacitor configuration

• US 7,939,415 B2
• Filed: 07/11/2008
• Issued: 05/10/2011
• Est. Priority Date: 01/31/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Richter, Ralf
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US12/171,633
• Publication Number:
  US 20090194844A1
• Time in Patent Office: 1,033 Days
• Field of Search: 438/131, 438/311, 438/386, 257/532, 257/E21.351, 257/E21.32, 257/E21.561
• US Class Current: 438/311
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

By forming a first portion of a substrate contact in an SOI device on the basis of a trench capacitor process, the overall manufacturing process for patterning contact elements may be enhanced since the contacts may only have to extend down to the level of the semiconductor layer. Since the lower portion of the substrate contact may be formed concurrently with the fabrication of trench capacitors, complex patterning steps may be avoided which may otherwise have to be introduced when the substrate contacts are to be formed separately from contact elements connecting to the device level.

Claims

1. A method, comprising:

forming a first trench in a first device region and a second trench in a second device region of an SOI semiconductor device, said first and second trenches extending from a height level approximately corresponding to a semiconductor layer through a buried insulating layer and into a substrate material of said SOI semiconductor device;

forming an insulating layer on an inner surface of said first and second trenches;

filling said first and second trenches with a conductive material;

forming a transistor element in and on said semiconductor layer;

forming an interlayer dielectric material above said transistor element;

forming a first contact element and a second contact element in said interlayer dielectric material, said first contact element establishing an electric connection to said conductive material formed in said first trench and said second contact element connecting to said transistor element; and

selectively establishing a conductive path between said substrate and said conductive material in said first trench so as to provide a substrate contact, wherein selectively establishing said conductive path comprises applying a voltage across said conductive material in said first trench and said substrate to induce an electric breakdown through said insulating layer in said first trench.

2. The method of claim 1, wherein said conductive path is established prior to forming said first and second contact elements.

3. The method of claim 1, wherein said conductive path is established after forming said first and second contact elements.

4. The method of claim 1, further comprising using said first trench as a discharge path during at least one manufacturing process.

5. The method of claim 1, wherein said second trench, including said insulating layer and said conductive material, is used as a capacitor.

6. The method of claim 5, wherein said second device region represents a region for forming a memory area and said capacitor represents a storage capacitor.

7. The method of claim 1, further comprising selectively providing a dopant species in said first device region so as to adapt a conductivity of said conductive path.

8. The method of claim 1, wherein a depth of said first and second trenches is approximately 1 μ

m or greater.

9. The method of claim 1, wherein forming said transistor element comprises forming at least one feature of said transistor element so as to have one lateral dimension of approximately 40 nm or less.

10. The method of claim 1, further comprising forming a metallization system above said transistor element and establishing said conductive path by supplying a voltage to said conductive material in said first trench via said metallization system.

11. The method of claim 1, wherein said first contact element is formed so as to be vertically above said first trench.

12. The method of claim 1, wherein said electric connection is established via said semiconductor layer.

13. A method of forming a substrate contact in an SOI device, the method comprising:

forming a first trench and a second trench so as to extend from a height level approximately corresponding to a semiconductor layer of said SOI device through a buried insulating layer and into a substrate material of said SOI device;

filling said first and second trenches with a dielectric liner and a conductive material to form a first structure acting as a capacitor and a second structure acting as a capacitor, said substrate representing a first electrode and said conductive material representing a second electrode in each of said first and second structures; and

selectively applying a voltage to said first structure so as to permanently damage said dielectric liner to establish a conductive path between said first electrode and said second electrode of the first structure.

14. The method of claim 13, further comprising forming a transistor element in and on said semiconductor layer, forming an interlayer dielectric material above said transistor element and forming a first contact and a second contact in said interlayer dielectric material in a common process sequence, said first contact electrically connecting to said first structure.

15. The method of claim 13, further comprising selectively adjusting at least one of a dopant concentration and a conductivity type at least in a portion of said substrate acting as said first electrode.

16. The method of claim 13, further comprising performing a manufacturing process and using said first structure as a discharge path for removing charges accumulating in said semiconductor layer during said manufacturing process.

17. The method of claim 14, further comprising forming a conductive element so as to electrically connect said transistor element with said second structure.