Pixel structure of a thin film transistor liquid crystal display and fabricating method thereof

• US 7,939,875 B2
• Filed: 07/16/2009
• Issued: 05/10/2011
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Huang, Tzufong, Huang, Mao-Tsun
• Primary Examiner(s): LOUIE, WAI SING
• Application Number:
  US12/504,056
• Publication Number:
  US 20090272977A1
• Time in Patent Office: 663 Days
• Field of Search: 257/257, 257/290, 257/300, 257/303
• US Class Current: 257/300
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.

Claims

1. A pixel structure of a thin film transistor liquid crystal display, comprising:

a thin film transistor disposed on a surface of a substrate, wherein the thin film transistor comprises a gate pattern, a gate insulating layer disposed on the gate pattern and the substrate, a semiconductor layer covering the gate insulating layer and a source pattern and a drain pattern formed over the semiconductor layer;

a pixel electrode pattern disposed on the surface of the substrate, wherein the pixel electrode pattern is electrically connected to the drain pattern of the thin film transistor;

a passivation layer covering the thin film transistor but exposing the pixel electrode pattern; and

a storage capacitor, disposed on the substrate, comprising a lower electrode, an upper electrode and a capacitor dielectric layer, wherein the lower electrode comprises a lower transparent conductive layer and an upper metallic layer, and the upper electrode covers a portion of the pixel electrode pattern.

2. The pixel structure of claim 1, wherein the drain pattern covers a portion of the pixel electrode pattern.

3. The pixel structure of claim 1, wherein the gate pattern comprises a lower transparent conductive layer and an upper metallic layer.

4. The pixel structure of claim 3, wherein the upper metallic layer comprises a single metallic layer, an alloy layer or a multi-layered metallic layer.

5. The pixel structure of claim 1, wherein the gate insulating layer in the thin film transistor is formed between the semiconductor layer and the gate pattern.

6. The pixel structure of claim 1, wherein the upper electrode covers a portion of the pixel electrode pattern.

7. The pixel structure of claim 1, wherein the pixel structure further comprises a bonding pad pattern disposed on two edges of the substrate.

8. The pixel structure of claim 7, wherein the bonding pad comprises a lower transparent conductive layer and an upper metallic layer, and the upper metallic layer exposes a portion of the lower transparent conductive layer.

10. The pixel structure of claim 1, wherein the drain pattern and the source pattern are single metallic layers, alloy layers or multi-layered metallic layers.

9. A pixel structure of a thin film transistor liquid crystal display, comprising:

a thin film transistor disposed on a surface of a substrate, wherein the thin film transistor comprises a gate pattern, a gate insulating layer disposed on the gate pattern and the substrate, a semiconductor layer covering the gate insulating layer and a source pattern and a drain pattern formed over the semiconductor layer;

a pixel electrode pattern disposed on the surface of the substrate, wherein the pixel electrode pattern is electrically connected to the drain pattern of the thin film transistor;

a passivation layer covering the thin film transistor but exposing the pixel electrode pattern;

a storage capacitor, disposed on the substrate, comprising a lower electrode, an upper electrode and a capacitor dielectric layer, wherein the lower electrode comprises a lower transparent conductive layer and an upper metallic layer; and

a bonding pad pattern disposed on two edges of the substrate, wherein the bonding pad comprises a lower transparent conductive layer and an upper metallic layer, the upper metallic layer exposes a portion of the lower transparent conductive layer, and the passivation layer exposes the lower transparent conductive layer of the bonding pad pattern.