SOI substrate contact with extended silicide area

• US 7,939,896 B2
• Filed: 11/06/2009
• Issued: 05/10/2011
• Est. Priority Date: 10/08/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Slinkman, James Albert, Doan, Thai, Levy, Max Gerald, Levy, Jessica Anne, Norris, Alan Frederick, Dang, Dinh
• Primary Examiner(s): Tran; Tan N
• Application Number:
  US12/613,631
• Publication Number:
  US 20100084736A1
• Time in Patent Office: 550 Days
• Field of Search: 257/377, 257/382, 257/383, 257/412, 257/413, 257/347, 257/774, 257/E29.156
• US Class Current: 257/377
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Claims

1. A structure, comprising:

dielectric isolation in an upper silicon layer of a substrate, said substrate comprising a buried oxide layer between said upper silicon layer and a lower silicon layer, said dielectric isolation coplanar with and extending from a top surface of said upper silicon layer to said buried oxide layer, said dielectric isolation completely surrounding a perimeter of a contact region;

a polysilicon region extending through said contact region and through said buried oxide layer to said lower silicon layer, said contact region completely surrounding a perimeter of said polysilicon region, said polysilicon region doped a same dopant type as said lower silicon layer; and

a contiguous metal silicide layer in remaining portions of said contact region and said polysilicon region, said metal silicide layer extending from a top surface of said polysilicon region into said polysilicon region and extending from a top surface of said remaining portions of said contact region into said remaining portions of said contact region.

2. The structure of claim 1, further including:

an enhanced contact region in said lower silicon layer, abutting a bottom of said polysilicon region, said enhanced contact region doped said same dopant type as said lower silicon layer.

3. The structure of claim 2, wherein an interface between said polysilicon region and said lower silicon layer has a resistivity of about 0.05 ohm-cm or less.

4. The structure of claim 1, further including:

a top surface of said polysilicon region recessed below a top surface of said dielectric isolation.

5. The structure of claim 1, wherein said lower silicon layer and said upper silicon layer are doped P-type.

6. The structure of claim 1, wherein a width of said polysilicon region measured in a direction parallel to a top surface of said upper silicon layer is less than a width of said contact region measured in said direction parallel to a top surface of said upper silicon layer.

7. The structure of claim 1, wherein a ratio of (i) a total thickness of said polysilicon region measured in a direction perpendicular to said top surface of said upper silicon layer to (ii) a width of said polysilicon region measured in a direction parallel to said top surface of said upper silicon layer is equal to or greater than about 3.

8. The structure of claim 1, wherein said polysilicon region does not physically contact said dielectric isolation.

9. The structure of claim 1, wherein at least a portion of said contact region intervenes between said dielectric isolation and said polysilicon region.

10. The structure of claim 1, wherein said contact region is in the form of a first ring surrounded by said dielectric isolation and said polysilicon region is in the form of a second ring within said first ring.