Chip packages with covers

• US 7,939,918 B2
• Filed: 10/26/2006
• Issued: 05/10/2011
• Est. Priority Date: 12/10/1999
• Status: Expired due to Term

• Current Assignee: Invensas Corporation
• Original Assignee: Tessera Technologies Ireland Limited (Adeia Inc.)
• Inventors: Badehi, Avner Pierre
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US11/588,489
• Publication Number:
  US 20070040257A1
• Time in Patent Office: 1,657 Days
• Field of Search: 257/433, 257666-738, 257/E23.018, 257/25.023, 257/29.022
• US Class Current: 257/666
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81B 7/0067 for controlling the passage of optical signals through the package
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/032 Gluing
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/16235 Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H03H 9/105 the enclosure being defined by a cover cap mounted on an element forming part of the BAW device
• CPC Class Codes: H03H 9/1057 for microelectro-mechanical devices
• CPC Class Codes: H03H 9/1092 the enclosure being defined by a cover cap mounted on an element forming part of the surface acoustic wave [SAW] device on the side of the IDT's

Abstract

This invention discloses a crystalline substrate based device including a crystalline substrate having formed thereon a microstructure; and at least one packaging layer which is sealed over the microstructure by means of an adhesive and defines therewith at least one gap between the crystalline substrate and the at least one packaging layer. A method of producing a crystalline substrate based device is also disclosed.

Claims

1. A unit comprising:

(a) an integrated circuit including a crystalline substrate having a microstructure, said integrated circuit having a front face and electrically conductive pads adjacent the front face;

(b) a cover overlying the front face of the integrated circuit, the cover being spaced from said front face so that said cover and said front face define at least one cavity therebetween, the cover and the integrated circuit cooperatively defining a chip scale package having planar surfaces and edge surfaces extending between the planar surfaces, the pads of the integrated circuit extending to at least some of the edge surfaces; and

(c) contacts connected to the pads extending along at least one of said edge surfaces and onto at least one of the planar surfaces.

2. A unit as claimed in claim 1 wherein said cover is sealed to said integrated circuit.

3. A unit as claimed in claim 1 further comprising an adhesive, the cover being sealed to the integrated circuit by the adhesive.

4. A unit as claimed in claim 1 wherein said cover is transparent.

5. A unit as claimed in claim 4 wherein said integrated circuit includes an optoelectronic device.

6. A unit as claimed in claim 5 further comprising an array of microlenses overlying the front surface of the integrated circuit within the cavity.

7. A unit as claimed in claim 4 wherein said integrated circuit includes a micromirror array.

8. A unit as claimed in claim 1 further comprising a spacer formed separately from the integrated circuit and the cover, the spacer being disposed between the integrated circuit and the cover.

9. A unit as claimed in claim 8 wherein the spacer surrounds the cavity.

10. A unit as claimed in claim 8 further comprising an adhesive extending between the integrated circuit and the cover in contact with the spacer.

11. A unit as claimed in claim 10 wherein the adhesive is disposed at the edge surfaces of the package.

12. A unit comprising:

(a) an integrated circuit including a crystalline substrate having a microstructure, said integrated circuit having a front face, a rear face, edges extending between the front and rear faces and electrically conductive pads adjacent the front face extending to at least some edges of the integrated circuit;

(b) a cover overlying the front face of the integrated circuit, the cover being spaced apart from said front face so that said cover and said front face define at least one cavity therebetween, the cover and the integrated circuit cooperatively defining a chip scale package; and

(c) contacts connected to the pads extending away from the cover along at least one of said edges of the integrated circuit and extending over the rear face of the integrated circuit.

13. A unit as claimed in claim 12 wherein said cover is sealed to said integrated circuit.

14. A unit as claimed in claim 12 further comprising an adhesive, the cover being sealed to the integrated circuit by the adhesive.

15. A unit as claimed in claim 12 wherein said cover is transparent.

16. A unit as claimed in claim 15 wherein said integrated circuit includes an optoelectronic device.

17. A unit as claimed in claim 16 further comprising an array of microlenses overlying the front surface of the integrated circuit within the cavity.

18. A unit as claimed in claim 15 wherein said integrated circuit includes a micromirror array.

19. A unit as claimed in claim 12 further comprising a spacer formed separately from the integrated circuit and the cover, the spacer being disposed between the integrated circuit and the cover.

20. A unit as claimed in claim 19 wherein the spacer surrounds the cavity.

21. A unit as claimed in claim 19 further comprising an adhesive extending between the integrated circuit and the cover in contact with the spacer.

22. A unit as claimed in claim 21 wherein the spacer is disposed inboard from the edges of the integrated circuit and the adhesive extends outwardly from the spacer to the edges of the integrated circuit.

23. A unit as claimed in claim 12 wherein at least some of the edges of the integrated circuit are oblique to the front face of the integrated circuit.

24. A unit as claimed in claim 12 further comprising a material overlying the edges of the integrated circuit, the contacts extending over said material.

25. A unit as claimed in claim 24 wherein the material is an epoxy.

26. A unit as claimed in claim 12 further comprising a packaging layer overlying the rear surface of the integrated circuit, the contacts extending over the packaging layer.