Low leakage and data retention circuitry
DCFirst Claim
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1. An integrated circuit comprising:
- two power supply terminals for powering of the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a Vss ground terminal together defining a range of logic levels;
cells in series with a sleep transistor electrically connected to one of said power supply terminals, each of said cells being either a logic gate or a storage cell;
generator circuitry configured to generate a variable voltage outside said range of logic levels; and
additional circuitry configured to apply, in a power down mode, said variable voltage to said sleep transistor.
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Abstract
An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.
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20 Claims
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1. An integrated circuit comprising:
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two power supply terminals for powering of the integrated circuit, said power supply terminals including a Vdd positive supply terminal and a Vss ground terminal together defining a range of logic levels; cells in series with a sleep transistor electrically connected to one of said power supply terminals, each of said cells being either a logic gate or a storage cell; generator circuitry configured to generate a variable voltage outside said range of logic levels; and additional circuitry configured to apply, in a power down mode, said variable voltage to said sleep transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A power management method comprising:
operating an integrated circuit having cells, each of the cells being a either a logic gate or a storage cell, said cells being in series with a sleep transistor electrically connected to a either a Vdd positive supply terminal or a Vss ground terminal, the Vdd'"'"' positive supply terminal and the Vss ground terminal together defining a range of logic levels, and the operating of the integrated circuit including; generating a variable voltage outside said range of logic levels; and applying, in a power down mode, said variable voltage to the sleep transistor. - View Dependent Claims (18, 19, 20)
Specification