Peak-detect-and-hold circuit and method thereof using ramp sampling technique

• US 7,940,089 B2
• Filed: 10/06/2009
• Issued: 05/10/2011
• Est. Priority Date: 09/04/2009
• Status: Expired due to Fees

• Current Assignee: National Tsing Hua University
• Original Assignee: National Tsing Hua University
• Inventors: Chou, Hwai-Pwu, Lin, Chien-Jen
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Chen; Sibin
• Application Number:
  US12/574,411
• Publication Number:
  US 20110057706A1
• Time in Patent Office: 581 Days
• Field of Search: None
• US Class Current: 327/60
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

A peak detect-and-hold circuit and method thereof using ramp sampling technique includes utilizing two sampling signals of different slopes to sample an input voltage for respective tracking voltages; comparing the held tracking voltage sampled with the sampling signal of a smaller slope and the input voltage to determine whether the input voltage is rising or falling, and if the input voltage starts falling, the held tracking voltage sampled with the sampling signal of a larger slope is taken as the peak. The peak detect-and-hold circuit using ramp sampling technique controls respective tracking voltages by comparing the input voltage with the sampling signals rather than the feedback tracking voltage. Also, it uses the input voltage directly rather than an operational transconductance amplifier to charge holding capacitors for the tracking voltages. Therefore, the errors of peak detecting and holding, namely the pedestal voltage, overshoot voltage and voltage droop are reduced.

Claims

1. A peak detect-and-hold circuit using ramp sampling technique for detecting and holding a peak voltage of an input voltage, wherein the peak detect-and-hold circuit comprises:

a sampling signal generator producing at least a first sampling signal and a second sampling signal, wherein the first sampling signal and the second sampling signal are rising waveforms, and the slope of the first sampling signal is greater than that of the second sampling signal;

a first comparator receiving the first sampling signal generated by the sampling signal generator and the input voltage;

a first sample-and-hold circuit wherein the first comparator controls the first sample-and-hold circuit to keep a first tracking voltage tracking the input voltage when the first sampling signal is less than the input voltage, and to sample the input voltage and hold the first tracking voltage at the sampled input voltage when the first sampling signal is equal to the input voltage;

a second comparator receiving the second sampling signal generated by the sampling signal generator and the input voltage;

a second sample-and-hold circuit wherein the second comparator controls the second sample-and-hold circuit to keep a second tracking voltage tracking the input voltage when the second sampling signal is less than the input voltage, and to sample the input voltage and hold the second tracking voltage at the sampled input voltage when the second sampling signal is equal to the input voltage; and

a third comparator receiving the second tracking voltage and the input voltage, wherein

when the second tracking voltage is smaller than the input voltage the third comparator triggers the sampling signal generator to generate another of the first sampling signal and another of the second sampling signal; and

when the second tracking voltage is greater than the input voltage, the first tracking voltage is taken as the peak voltage.

2. The peak detect-and-hold circuit according to claim 1, wherein the rising waveforms are linear or nonlinear.

3. The peak detect-and-hold circuit according to claim 2, wherein the rising waveforms are ramps.

4. The peak detect-and-hold circuit according to claim 3, wherein the slope of the first sampling signal is approximately two times the slope of the second sampling signal.

5. The peak detect-and-hold circuit according to claim 1, wherein the slopes of the first sampling signal and the second sampling signal are within 1% of the input voltage amplitude over its peaking time.

6. The peak detect-and-hold circuit according to claim 1, wherein the first sample-and-hold circuit is a non-feedback type of sample-and-hold circuit.

7. The peak detect-and-hold circuit according to claim 1, wherein the second sample-and-hold circuit is a non-feedback type of sample-and-hold circuit.

8. A peak detect-and-hold method using ramp sampling technique for detecting and holding a peak voltage of an input voltage, wherein the peak detect-and-hold method comprises:

generating at least a first sampling signal and a second sampling signal, wherein the first sampling signal and the second sampling signal are rising waveforms, and the slope of the first sampling signal is greater than that of the second sampling signal;

comparing the first sampling signal and the input voltage, wherein when the first sampling signal is smaller than the input voltage, the first tracking voltage is kept tracking the input voltage, and when the first sampling signal is equal to the input voltage, the input voltage is sampled and the first tracking voltage is held at the sampled input voltage;

comparing the second sampling signal and the input voltage, wherein when the second sampling signal is smaller than the input voltage, the second tracking voltage is kept tracking the input voltage, and when the second sampling signal is equal to the input voltage, the input voltage is sampled and the second tracking voltage is held at the sampled input voltage; and

comparing the second tracking voltage and the input voltage, wherein

when the second tracking voltage is smaller than the input voltage, another of the first sampling signal and another of the second sampling signal are generated so as to proceed with the comparing steps; and

when the second tracking voltage is greater than the input voltage, the first tracking voltage is taken as the peak voltage.

9. The peak detect-and-hold method according to claim 8, wherein the rising waveforms are linear or nonlinear.

10. The peak detect-and-hold method according to claim 9, wherein the rising waveforms are ramps.

11. The peak detect-and-hold method according to claim 10, the slope of the first sampling signal is approximately two times the slope of the second sampling signal.

12. The peak detect-and-hold method according to claim 8, the slopes of the first sampling signal and the second sampling signal are within 1% of the input voltage amplitude over its peaking time.

13. The peak detect-and-hold method according to claim 8, wherein the first tracking voltage and the second tracking voltage are generated by a first sample-and-hold circuit and a second sample-and-hold circuit, respectively.

14. The peak detect-and-hold method according to claim 13, the first sample-and-hold circuit is a non-feedback type of sample-and-hold circuit.

15. The peak detect-and-hold method according to claim 13, the second sample-and-hold circuit is a non-feedback type of sample-and-hold circuit.