Gate driver circuit for H bridge circuit

• US 7,940,092 B2
• Filed: 09/08/2009
• Issued: 05/10/2011
• Est. Priority Date: 09/28/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Li, Waley, Li, Weiying, Zhao, Hongwei, Wei, Linpeng, Zheng, Iven
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US12/554,995
• Publication Number:
  US 20100079194A1
• Time in Patent Office: 609 Days
• Field of Search: 327/110, 327/423, 327/588
• US Class Current: 327/110
• CPC Class Codes: H02M 7/538 in a push-pull configuration H02M7/5375 takes precedence ; with oscillating arrangements H02M7/53832, H02M7/53846
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches

Abstract

An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with V_G=0 in a conventional H bridge circuit.

Claims

1. An H bridge circuit, comprising:

a first P-channel Metal Oxide Semiconductor (PMOS) device;

a first N-channel Metal Oxide Semiconductor (NMOS) device, the first PMOS device and the first NMOS device being coupled in series between a voltage source and a ground (GND);

a gate driver for the first PMOS device, coupled to a gate of the first PMOS device; and

a gate driver circuit for the first NMOS device, coupled to a gate of the first NMOS device, wherein the output of the gate driver circuit for the first NMOS device is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit, and

wherein the gate driver circuit for the first NMOS device comprises;

a driver having an output;

an amplifier (AMP) having a non-inverting input at a voltage from 0.1V to 0.4V, an inverting input coupled to the gate of the first NMOS device, and an output; and

a switch circuit that includes a first switch and a second switch, wherein the output of the driver is provided to the gate of the first NMOS device via the first switch and the output of the AMP is provided to the gate of the first NMOS device via the second switch, and

wherein the first switch is open and the second switch is closed during the dead time of the H bridge circuit.

2. The H bridge circuit of claim 1, wherein the output of the gate driver circuit for the first NMOS device is at a voltage of 0.4V.

3. The H bridge circuit of claim 1, wherein the inverting input of the AMP is coupled to the gate of the first NMOS device via the second switch.

4. The H bridge circuit of claim 1, wherein:

the driver comprises two pre-drivers, the first switch comprises two first switches, and the second switch comprises two second switches,

the gate driver circuit for the first NMOS device further comprises a second PMOS device and a second NMOS device coupled with each other in series between the voltage source and the GND,

the outputs of the two pre-drivers are coupled to a gate of the second PMOS device and a gate of the second NMOS device, respectively, via the two first switches,

the output of the AMP is coupled to the gate of the second PMOS device and the gate of the second NMOS device, respectively, via the two second switches, and

the output of the gate driver circuit for the first NMOS device is provided at a node between the second PMOS device and the second NMOS device, and the inverting input of the AMP is directly coupled to the gate of the first NMOS device.

5. A gate driver circuit for an N-channel Metal Oxide Semiconductor (NMOS) device in an H bridge circuit, comprising:

a driver;

an amplifier (AMP), wherein a non-inverting input of the AMP is at a voltage from 0.1V to 0.4V, and an inverting input of the AMP is coupled to a gate of the NMOS device; and

a switch circuit that includes a first switch and a second switch, wherein an output of the driver is provided to the gate of the NMOS device via the first switch and the output of the amplifier is provided to the gate of the NMOS device via the second switch,

wherein the first switch is open and the second switch is closed during a dead time of the H bridge circuit.

6. The gate driver circuit of claim 5, wherein the inverting input of the AMP is coupled to the gate of the first NMOS device via the second switch.

7. The gate driver circuit of claim 5, wherein:

the driver comprises two pre-drivers, the first switch comprises two first switches, and the second switch comprises two second switches;

the gate driver circuit further comprises a P-channel Metal Oxide Semiconductor (PMOS) device and a second NMOS device coupled with each other in series between a voltage source and a GND;

the outputs of the two pre-drivers are coupled to a gate of the PMOS device and a gate of the second NMOS device, respectively, via the two first switches;

the output of the AMP is coupled to the gate of the PMOS device and the gate of the second NMOS device, respectively, via the two second switches; and

the output of the gate driver circuit is provided at a point connected between the PMOS device and the second NMOS device, and the inverting input of the AMP is directly coupled to the gate of the first NMOS device.