Memory system having multiple vias at junctions between traces
First Claim
1. An improvement to a memory system having a hierarchical bitline structure that includes a first global write line configured to carry a first global write signal and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the first global write line includes first and third traces and the second global write line includes second and fourth traces, wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer, wherein the improvement comprises:
- at least one of the first and third traces having a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias;
at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap;
wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width.
1 Assignment
0 Petitions
Accused Products
Abstract
An improvement to a memory system having a hierarchical bitline structure wherein traces that form global write lines are connected to each other using junctions that include multiple vias to reduce capacitance and increase yield. At least one of a pair of traces connected by the vias includes a widened portion that provides sufficient overlap with the other trace to allow the two or more vias to be formed between the traces at the overlap. Parallel traces for global write lines that carry a write signal and its inverse may be positioned more than one maximum-density grid space apart to allow the widened portions to be formed between the traces. A global read line that is formed in a different metal layer from the global write line traces may be positioned in a grid space between the global write line traces to reduce the capacitance of this line.
-
Citations
18 Claims
-
1. An improvement to a memory system having a hierarchical bitline structure that includes a first global write line configured to carry a first global write signal and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the first global write line includes first and third traces and the second global write line includes second and fourth traces, wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer, wherein the improvement comprises:
-
at least one of the first and third traces having a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias; at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap; wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width. - View Dependent Claims (2, 3, 4, 5, 9)
-
-
6. An improvement to a memory system having a hierarchical bitline structure that includes a first global write line configured to carry a first global write signal and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the first global write line includes first and third traces and the second global write line includes second and fourth traces, wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer, wherein the improvement comprises:
-
at least one of the first and third traces having a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias; at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap; wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space. - View Dependent Claims (7, 8)
-
-
10. A memory system comprising:
-
a plurality of memory cells interconnected according to a hierarchical bitline structure; a first global write line configured to carry a first global write signal, wherein the first global write line includes first and third traces; and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the second global write line includes second and fourth traces; wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer; wherein at least one of the first and third traces has a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias, and wherein the first global write line includes at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap; and wherein the first and third traces have a nominal width and wherein the widened portion is at least twice the nominal width. - View Dependent Claims (11, 12, 13, 14, 18)
-
-
15. A memory system comprising:
-
a plurality of memory cells interconnected according to a hierarchical bitline structure; a first global write line configured to carry a first global write signal, wherein the first global write line includes first and third traces; and a second global write line configured to carry a second global write signal that is the inverse of the first global write signal, wherein the second global write line includes second and fourth traces; wherein each of the first and second traces is formed in a first metal layer of an integrated circuit (IC) and each of the third and fourth traces is formed in a second metal layer of the IC which is different from the first metal layer; wherein at least one of the first and third traces has a widened portion that has sufficient overlap with the other of the first and third traces to accommodate at least two vias, and wherein the first global write line includes at least two substantially adjacent vias connecting the first and third traces where the first and third traces overlap; and wherein the first and second traces are parallel to each other and are separated by more than one maximum-density grid space. - View Dependent Claims (16, 17)
-
Specification