Shared bit line and source line resistive sense memory structure

• US 7,940,548 B2
• Filed: 07/13/2009
• Issued: 05/10/2011
• Est. Priority Date: 07/13/2009
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Li, Hai, Liu, Hongyue, Wang, Xuguang
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/502,210
• Publication Number:
  US 20110007549A1
• Time in Patent Office: 666 Days
• Field of Search: 365/148, 365/100, 365/173, 365/145, 365/158, 365/196
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A resistive sense memory apparatus includes a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element and a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element. A bit line is electrically connected to the first resistive sense memory element and the second resistive sense memory element.

Claims

1. A resistive sense memory apparatus comprising:

a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element;

a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element; and

a bit line electrically connected to the first resistive sense memory element and the second resistive sense memory element.

2. A resistive sense memory apparatus according to claim 1, wherein the first semiconductor transistor and the second semiconductor transistor adjacent to each other and electrically isolated from each other.

3. A resistive sense memory apparatus according to claim 1, further comprising a third semiconductor transistor adjacent to the first semiconductor transistor, the third semiconductor transistor sharing the first contact electrically connected to the first source line, the third semiconductor transistor having a second contact electrically connected to a third resistive sense memory element.

4. A resistive sense memory apparatus according to claim 3, wherein the third semiconductor transistor and the first semiconductor transistor have a common source contact region.

5. A resistive sense memory apparatus according to claim 1, further comprising a fourth semiconductor transistor having a first contact electrically connected to a third source line and a second contact electrically connected to a forth resistive sense memory element, a second bit line electrically connected to the third resistive sense memory element and the fourth resistive sense memory element.

6. A resistive sense memory apparatus according to claim 1, wherein the first resistive sense memory element and the second resistive sense memory element comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

7. A resistive sense memory apparatus according to claim 1, wherein the first resistive sense memory element and the second resistive sense memory element are memory elements of a memory array.

8. A resistive sense memory apparatus according to claim 5, wherein the first semiconductor transistor, second semiconductor transistor, third semiconductor transistor, and fourth semiconductor transistor are electrically connected to a common word line.

9. A resistive sense memory apparatus comprising:

a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element;

a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element;

a bit line electrically connected to the first resistive sense memory element and the second resistive sense memory element; and

a third semiconductor transistor sharing the first contact electrically connected to the first source line, the third semiconductor transistor having a second contact electrically connected to a third resistive sense memory element, and the third resistive sense memory element electrically connected to a second bit line.

10. A resistive sense memory apparatus according to claim 9, further comprising a fourth semiconductor transistor having a first contact electrically connected to a third source line and a second contact electrically connected to a forth resistive sense memory element, the second bit line electrically connected to the third resistive sense memory element and the fourth resistive sense memory element.

11. A resistive sense memory apparatus according to claim 10, wherein the first semiconductor transistor and the second semiconductor transistor are adjacent to each other and electrically isolated from each other and the third semiconductor transistor and the fourth semiconductor transistor are adjacent to each other and electrically isolated from each other.

12. A resistive sense memory apparatus according to claim 9, wherein the first resistive sense memory element and the second resistive sense memory element comprise magnetic tunnel junctions switchable between a high resistance data state and a low resistance data state by spin torque transfer of a polarized current through the magnetic tunnel junction.

13. A resistive sense memory apparatus according to claim 9, wherein the first resistive sense memory element and the second resistive sense memory element are memory elements of a memory array.

14. A resistive sense memory apparatus according to claim 10, wherein the first semiconductor transistor, second semiconductor transistor, third semiconductor transistor, and fourth semiconductor transistor are electrically connected to a common word line.

15. A method of accessing a single resistive sense memory cell in a memory array comprising:

providing a resistive sense memory array comprising;

a first semiconductor transistor having a first contact electrically connected to a first source line and a second contact electrically connected to a first resistive sense memory element;

a second semiconductor transistor having a first contact electrically connected to a second source line and a second contact electrically connected to a second resistive sense memory element;

a bit line electrically connected to the first resistive sense memory element and the second resistive sense memory element; and

a third semiconductor transistor sharing the first contact electrically connected to the first source line, the third semiconductor transistor having a second contact electrically connected to a third resistive sense memory element, and the third resistive sense memory element electrically connected to a second bit line;

applying a source voltage to the first source line and the second bit line;

applying a drain voltage to the first bit line and second source line; and

applying a gate voltage to the word line to flow current through only the first resistive sense memory element.

16. A method according to claim 15, wherein the current is a read current.

17. A method according to claim 15, wherein the current is a write current.

18. A method according to claim 15, wherein source lines adjacent to the first source line and second source line are floating.

19. A method according to claim 15, wherein bit lines adjacent to the first bit line and second bit line are floating.