NAND flash memory having multiple cell substrates
First Claim
1. A NAND Flash memory comprising:
- a first well sector having a first NAND cell string for selectively receiving an erase voltage during an erase operation;
a second well sector having a second NAND cell string for selectively receiving the erase voltage during the erase operation;
a bitline electrically connected to the first NAND cell string and the second NAND cell string; and
,a page buffer electrically connected to the bitline.
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Accused Products
Abstract
A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
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Citations
29 Claims
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1. A NAND Flash memory comprising:
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a first well sector having a first NAND cell string for selectively receiving an erase voltage during an erase operation; a second well sector having a second NAND cell string for selectively receiving the erase voltage during the erase operation; a bitline electrically connected to the first NAND cell string and the second NAND cell string; and
,a page buffer electrically connected to the bitline. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A NAND Flash memory comprising:
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at least two well sectors each including at least one memory block of NAND cell strings, the at least one memory block in each of the at least two well sectors being electrically connected to corresponding bitline segments; and isolation devices coupled between the bitline segments corresponding to the at least two well sectors. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method for erasing a selected memory block in a NAND Flash device, comprising:
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selecting a memory block in a first well sector, the first well sector including at least two memory blocks electrically coupled to at least two memory blocks in a second well sector by a logical bitline; biasing the memory block formed in the first well sector for erasure; biasing an unselected memory block formed in the first well sector for inhibiting erasure; applying an erase voltage to the first well sector; and
,inhibiting application of the erase voltage to the second well sector. - View Dependent Claims (28, 29)
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Specification