Dual port memory device
First Claim
1. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising:
- a first storage module comprising a first storage node;
a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline;
a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline; and
a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode;
a reference node to provide a precharge signal;
a fourth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the first bit line, and a control electrode;
a fifth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the second bit line, and a control electrode; and
a control module coupled to the control electrode of the fifth transistor and operable, in response to a dummy access of the first storage module at the second transistor, to deactivate the fifth transistor during the dummy access of the first bit cell.
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Accused Products
Abstract
A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.
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Citations
18 Claims
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1. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising:
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a first storage module comprising a first storage node; a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline; a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline; and a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode; a reference node to provide a precharge signal; a fourth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the first bit line, and a control electrode; a fifth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the second bit line, and a control electrode; and a control module coupled to the control electrode of the fifth transistor and operable, in response to a dummy access of the first storage module at the second transistor, to deactivate the fifth transistor during the dummy access of the first bit cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
- terminating a precharge at a first bit line of a first port of a multi-port cell in response to determining an occurrence of a dummy access at the first port, and equalizing the first bit line of the first port of the multi-port cell to a second bit line of a second port of the multi-port cell in response to determining the occurrence of the dummy access at the first port.
- View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising:
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a first storage module comprising a first storage node and a second storage node; a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline; a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline; a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode; a fourth transistor comprising a first current electrode coupled to the second storage node, a second current electrode coupled to a third bit line, and a control electrode coupled to the first wordline; a fifth transistor comprising a first current electrode coupled to the second storage node, a second current electrode coupled to a fourth bit line, and a control electrode coupled to the second wordline; a sixth transistor comprising a first current electrode coupled to the third bit line, a second current electrode coupled to the fourth bit line, and a control electrode; and a seventh transistor comprising a first current electrode coupled to a voltage reference for precharging the first bit line, a second current electrode coupled to the first bit line, and a control electrode coupled to a control circuit, the control circuit to terminate a precharge at the first bit line in response to a dummy access to the first storage node.
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Specification