Dual port memory device

• US 7,940,599 B2
• Filed: 03/16/2009
• Issued: 05/10/2011
• Est. Priority Date: 03/16/2009
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Childs, Lawrence F., Lu, Olga R., Liston, Thomas W.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US12/404,892
• Publication Number:
  US 20100232202A1
• Time in Patent Office: 785 Days
• Field of Search: 365/230.05
• US Class Current: 365/230.05
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor.

Claims

1. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising:

a first storage module comprising a first storage node;

a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline;

a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline; and

a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode;

a reference node to provide a precharge signal;

a fourth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the first bit line, and a control electrode;

a fifth transistor comprising a first current electrode coupled to the reference node, a second current electrode coupled to the second bit line, and a control electrode; and

a control module coupled to the control electrode of the fifth transistor and operable, in response to a dummy access of the first storage module at the second transistor, to deactivate the fifth transistor during the dummy access of the first bit cell.

2. The device of claim 1 wherein the control module is further coupled to the control electrode of the third transistor and operable, in response to a dummy access of the first bit cell, to activate the third transistor.

3. The device of claim 2, wherein the control module is further operable in response to the dummy access of the first bit cell and a write access of the first bit cell, to activate the third transistor during the dummy access of the first storage cell.

4. The device of claim 1, wherein the control module is further operable to deactivate the fifth transistor in response to the dummy access of the first bit cell and a write access of the first bit cell.

5. The device of claim 4, wherein the control module is further operable to deactivate the fifth transistor in response to the dummy access of the first bit cell and the write access of the first bit cell occurring concurrently.

6. The device of claim 1, wherein the control module is operable, in response to access inactivity at the second word line, to activate the fifth transistor during the access inactivity.

7. The device of claim 1 the control module further coupled to the control electrode of the third transistor and operable, in response to a dummy access of the first storage cell occurring concurrently with a write access of the first storage cell, to activate the third transistor.

8. A method comprising:

terminating a precharge at a first bit line of a first port of a multi-port cell in response to determining an occurrence of a dummy access at the first port, and equalizing the first bit line of the first port of the multi-port cell to a second bit line of a second port of the multi-port cell in response to determining the occurrence of the dummy access at the first port.

9. The method of claim 8, wherein equalizing the first bit line to the second bit line is in response to the occurrence of the dummy access at the first port and an occurrence of a write access at the second port of the multi-port bit cell.

10. The method of claim 9, wherein equalizing the first bit line to the second bit line is in response to the dummy access and the write access being concurrent.

11. The method of claim 8, wherein terminating the precharge is further in response to the occurrence of a write access at a second port of the multi-port bit cell.

12. The method of claim 11, wherein the terminating the precharge is in response to the dummy access and the write access being concurrent.

13. The method of claim 8 further comprising:

maintaining the precharge at the first bit line in response to detecting access inactivity at the second port.

14. The method of claim 9 further comprising:

negating a signal provided to a word line of the first port in response to the dummy access being a read access and the dummy access occurring concurrently with the write access.

15. The method of claim 14 further comprising:

asserting the signal provided to the word line of the first port in response to the read access prior to negating the signal.

16. The method of claim 9 further comprising:

asserting a signal provided to a word line of the first port in response to a write access at the first port of the multi-port bit cell; and

maintaining a negated signal at a word line of a second port of the multi-port bit cell in response to a read access request to the second port of the multi-port bit cell occurring while the signal provided to the word line of the first port is asserted.

17. The method of claim 16, further comprising:

asserting the signal at the word line of the second port upon completion of the write access at the first port.

18. A device comprising a plurality of bit cells, a first bit cell of the plurality of bit cells comprising:

a first storage module comprising a first storage node and a second storage node;

a first transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a first bit line, and a control electrode coupled to a first wordline;

a second transistor comprising a first current electrode coupled to the first storage node, a second current electrode coupled to a second bit line, and a control electrode coupled to a second wordline;

a third transistor comprising a first current electrode coupled to the first bit line, a second current electrode coupled to the second bit line, and a control electrode;

a fourth transistor comprising a first current electrode coupled to the second storage node, a second current electrode coupled to a third bit line, and a control electrode coupled to the first wordline;

a fifth transistor comprising a first current electrode coupled to the second storage node, a second current electrode coupled to a fourth bit line, and a control electrode coupled to the second wordline;

a sixth transistor comprising a first current electrode coupled to the third bit line, a second current electrode coupled to the fourth bit line, and a control electrode; and

a seventh transistor comprising a first current electrode coupled to a voltage reference for precharging the first bit line, a second current electrode coupled to the first bit line, and a control electrode coupled to a control circuit, the control circuit to terminate a precharge at the first bit line in response to a dummy access to the first storage node.