Fully adaptive equalization for high loss communications channels

• US 7,940,839 B2
• Filed: 01/26/2005
• Issued: 05/10/2011
• Est. Priority Date: 01/26/2004
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Diablo Technologies Incorporated (Rambus Inc.)
• Inventors: Lapointe, Marcel, Badalone, Riccardo, Vareljian, Albert
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Wong; Linda
• Application Number:
  US10/597,455
• Publication Number:
  US 20080260016A1
• Time in Patent Office: 2,295 Days
• Field of Search: 375229-236, 375/340, 375/341
• US Class Current: 375/229
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04L 2025/03356 Baseband transmission
• CPC Class Codes: H04L 2025/03636 Algorithms using least mean square [LMS]
• CPC Class Codes: H04L 25/0307 using blind adaptation
• CPC Class Codes: H04L 25/03159 operating in the frequency domain H04L25/03165, H04L25/03178 take precedence
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.

Claims

1. An equalization apparatus for automatically equalizing serial communication over a communication channel comprising:

i) an adaptive transmit equalizer to receive an outgoing serial data stream and provide launch data into the communication channel, the launch data equalized in response to transmit control parameters;

ii) an adaptive receive equalizer to receive an incoming data stream from the communication channel and condition the received incoming data stream to produce an equalized output serial data stream in response to receive control parameters; and

iii) control means operable to control said adaptive transmit equalizer and said adaptive receive equalizer based on said incoming data stream;

wherein the adaptive receive equalizer includes an adaptive linear equalizer in combination with an adaptive non-linear decision feedback equalizer (DFE) to condition the received incoming data into said equalized output serial data stream; and

wherein the control means includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said transmit control parameters and said receive control parameters.

2. The apparatus of claim 1, wherein the adaptive transmit equalizer has a symbol spaced feed forward equalizer with two taps corresponding to a cursor and pre-cursor.

3. The apparatus of claim 1, wherein the adaptive transmit equalizer has a two co-efficient Finite Impulse Response (FIR) filter symbol spaced feed forward equalizer with two taps corresponding to a cursor and pre-cursor the output of which is the launch data.

4. The apparatus of claim 1, wherein the adaptive transmit equalizer has a symbol spaced feed forward equalizer with a tap corresponding to a cursor and M pre-cursor taps.

5. The apparatus of claim 1, wherein the adaptive transmit equalizer has an M co-efficient Finite Impulse Response VA) filter that sums a portion of a cursor and the output of a symbol spaced feed forward equalizer with M taps, each tap corresponding to a successively earlier pre-cursor up to an Mth pre-cursor to produce the launch data.

6. The apparatus of claim 1, wherein said linear equalizer includes two distinct signal paths to condition the received incoming data, one signal path is a controllable pure gain stage and the other signal path is independently controllable pure gain stage coupled to a high-pass filter, the combined output of both is gain adjusted and supplied to said adaptive non-linear decision feedback equalizer (DFE).

7. The apparatus of claim 1, wherein said DFE has a plurality of symbol spaced taps, each of which can be programmed independently.

8. The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream wherein said transmit control parameters and receive control parameters are determined by the bit values.

9. The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data wherein said transmit control parameters and receive control parameters are determined by the bit values in said window of data.

10. The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data wherein said transmit control parameters and receive control parameters are determined by the bit values in said window of data.

11. An equalization apparatus for automatically equalizing serial communication over a communication channel comprising:

i) an adaptive transmit equalizer including a symbol spaced feed forward equalizer with a first tap to condition a cursor symbol corresponding to a tap parameter C₀ and M additional taps to condition each successively earlier pre-cursor symbol corresponding to a respective tap parameter C<sub>−

M</sub> . . . C<sub>−

1</sub> to receive an outgoing serial data stream and output launch data into the communication channel;

ii) an adaptive receive equalizer to receive an incoming data stream from the communication channel including;

a controllable filter including a high-pass filter coupled to a controllable pure gain stage to condition the received incoming data stream corresponding to a gain parameter G_HF ;

a summing node to sum the output of said controllable filter with the received incoming data stream that is gain adjusted corresponding to a gain parameter G_DC;

a controllable pure gain stage coupled to the output of said summing node to provide an output at a gain corresponding to a gain parameter G_AGC;

an N tap adaptive non-linear decision feedback equalizer (DFE) coupled to the output of the G_AGC stage providing N symbol spaced taps, each of which can be programmed independently corresponding to a respective tap parameter C₁, C₂ . . . C_N; and

iii) a demux and tap update block controller coupled to the output of said adaptive receive equalizer to produce said gain and tap parameters G_HF, G_AGC and C<sub>−

1</sub> , C₀ . . . C_N.

12. The apparatus of claim 11 wherein said demux and tap update block controller further includes a data slicer, a positive offset monitor slicer and a negative offset monitor slicer each coupled to the output of said adaptive receiver.

13. The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said gain and tap parameters.

14. The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data in said data demultiplexer, said positive monitor demultiplexer and said negative monitor demultiplexer wherein said gain and tap parameters are determined by the bit values in said window of data.

15. The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data in said data demultiplexer, said positive monitor demultiplexer and said negative monitor demultiplexer wherein said gain and tap parameters are determined by the bit values in said window of data.

16. The apparatus of claim 11 wherein said demux and tap update block controller includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data in said data word, said positive monitor word and said negative monitor word wherein said gain and tap parameters are determined by the bit values.

17. The apparatus of claim 11 wherein said demux and tap update block controller includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data in said data word, said positive monitor word and said negative monitor word wherein said gain and tap parameters are determined by the bit values.

18. A method for automatically equalizing serial communication over a communication channel comprising the steps of:

i) using an M tap feed forward equalizer to shape an outgoing data stream into a launch data stream based on a respective pre-cursor symbol tap parameter C<sub>−

M</sub> . . . C₁₋

and a symbol tap parameter C₀;

ii) supplying the launch data stream to the communication channel;

iii) receiving an incoming data stream from the communication channel;

iv) conditioning the received incoming data stream by passing the incoming data stream through an adaptive linear equalizer and an N Tap Decision Feedback Equalizer (DFE) with corresponding symbol spaced tap parameters [C<sub>−

M</sub>;

C_N] to produce an equalized serial data stream;

v) sampling the equalized serial data stream to latch user data;

vi) sampling the equalized serial data stream to latch monitor data; and

vii) producing the tap parameters [C<sub>−

M</sub>;

C_N] from the user data and monitor data;

further including a step of producing gain parameters G_DC, G_HF and G_AGC from the user data and monitor data, and wherein the step of conditioning the received incoming data stream by passing the incoming data stream through an adaptive linear equalizer includes;

i) supplying the incoming data stream to a first signal path through a high-pass filter coupled to a controllable pure gain stage at a gain corresponding to a gain parameter G_HF and to a second signal path through a controllable pure gain stage coupled at a gain corresponding to a gain parameter G_DC;

ii) summing the outputs of said first and second signal paths; and

iii) supplying the said sum of the outputs to a controllable pure gain stage at a gain corresponding to a gain parameter G_AGC to produce the input for said an N Tap Decision Feedback Equalizer (DFE).

19. The method of claim 18 further including the steps of:

i) over a plurality of symbol periods;

storing the latched user data in a data channel word;

storing the latched monitor data in a monitor channel word; and

ii) producing the symbol spaced tap parameters from selected portions of said stored user data and said stored monitor data.

20. The method of claim 19 further including the step of generating a bit offset to define a window of data in said data channel word and said monitor channel word whereby the step of producing the symbol spaced tap parameters is based on said data window defining said selected portions of said stored user data and said stored monitor data determined by said bit offset.

21. The method of claim 20 wherein a pseudo random bit offset is generated each time said symbol spaced tap parameters are produced.