Data reproduction circuit

• US 7,940,873 B2
• Filed: 02/23/2006
• Issued: 05/10/2011
• Est. Priority Date: 09/16/2005
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka
• Primary Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US11/359,504
• Publication Number:
  US 20070064850A1
• Time in Patent Office: 1,902 Days
• Field of Search: 375/354, 375/355, 375/371, 375/373, 375/375, 375/376
• US Class Current: 375/355
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

Claims

1. A data reproduction circuit for receiving data and reproducing data and a clock, comprising:

an over-sampling determination circuit for sampling the received data by a first reproduced clock with a frequency higher than a data rate of the received data, so as to convert the received data into digital signals;

a data selection circuit having a first circuit for reproducing data from the digital signals based on the first reproduced clock and for outputting the data, and having a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference between the first reproduced clock and the digital signals so as to generate and output an adjustment signal based on the phase error and the frequency error; and

a clock generation circuit having a phase/frequency adjustment circuit for adjusting a phase and a frequency of the first reproduced clock using the adjustment signal,

wherein the clock generation circuit provides the first reproduced clock having an adjusted phase and adjusted frequency to the over-sampling determination circuit and the data selection circuit,

wherein the phase/frequency error detection circuit detects a data change timing of the over-sampled data based on the first reproduced clock, generates a phase signal from the data change timing, converts the phase signal into a pointer signal that indicates movement of the phase signal, and outputs the pointer signal as the adjustment signal in order to adjust a phase of the first reproduced clock.

2. The data reproduction circuit according to claim 1, wherein:

the phase/frequency adjustment circuit is a phase interpolator; and

wherein the data reproduction circuit further comprises a digital filter for generating a weighting signal which controls the phase interpolator on the basis of the adjustment signal of the phase/frequency error detection circuit and for outputting the weighting signal to the phase interpolator.

3. The data reproduction circuit according to claim 1, wherein the frequency/phase error detection circuit generates a signal for adjusting a frequency from the pointer signal, and outputs the signal for adjusting a frequency and the adjustment signal for adjusting a phase.

4. The data reproduction circuit according to claim 1, wherein the phase/frequency error detection circuit includes a charge pump and a loop filter, and a current source of the charge pump is controlled and switched by the pointer signal such that an output of the charge pump is converted into the adjustment signal by the loop filter.

5. A data reproduction circuit for receiving data and reproducing data and a clock, comprising:

an over-sampling determination circuit for sampling the received data by a first reproduced clock with a frequency higher than a data rate of the received data, so as to convert the received data into digital signals;

a data selection circuit having a first circuit for reproducing data from the digital signals based on the first reproduced clock and for outputting the data, and having a phase/frequency error detection circuit for detecting a phase error and a frequency error from a timing difference between the first reproduced clock and the digital signals so as to generate and output an adjustment signal based on the phase error and the frequency error; and

a clock generation circuit having a phase/frequency adjustment circuit for adjusting a phase and a frequency of the first reproduced clock using the adjustment signal,

wherein the clock generation circuit provides the first reproduced clock having an adjusted phase and adjusted frequency to the over-sampling determination circuit and the data selection circuit,

wherein the phase/frequency error detection circuit performs a phase detect process and a phase generation control process (in a cycle 0), a phase generate process (in a cycle 1), an up/down (U/D) generate process (in a cycle, 2), a pointer generate process (in a cycle 3), a decode process and a charge pump control process (in a cycle 4) in a pipeline process based on the first reproduced clock.