Partitioned radio-frequency apparatus and associated methods

• US 7,941,102 B2
• Filed: 10/31/2007
• Issued: 05/10/2011
• Est. Priority Date: 01/12/2001
• Status: Expired due to Term

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Behrens, Richard T., Vishakhadatta, G. Diwakar, Srinivasan, Vishnu Shankar, Scott, Jeffrey W., Tuttle, G. Tyson, Kerth, Donald A.
• Primary Examiner(s): LEE, JOHN J
• Application Number:
  US11/931,656
• Publication Number:
  US 20080139157A1
• Time in Patent Office: 1,287 Days
• Field of Search: 455/75, 455/74, 455/191.1, 455/313, 455/552.1, 455/114.2, 455/86, 455/77, 455/78, 455/83, 455/87, 455/88, 455/553.1, 455/138, 455/139, 455/147, 455/232.1, 455/189.1, 455/163.2, 455/255, 455/234.1, 375/334, 375/316, 375/322
• US Class Current: 455/75
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Claims

1. A radio-frequency (RF) apparatus, comprising:

a first integrated circuit, comprising;

a low-noise amplifier (LNA), the low-noise amplifier configured to receive a radio-frequency (RF) signal, and to provide an amplified radio-frequency (RF) signal;

a down-converter coupled to the low-noise amplifier (LNA), the down-converter configured to mix the radio-frequency (RF) signal with a local-oscillator signal to generate an in-phase signal and a quadrature signal; and

a complex analog-to-digital converter (ADC) coupled to the down-converter, the analog-to-digital converter (ADC) configured to convert the in-phase signal to a one-bit in-phase digital signal, the analog-to-digital converter (ADC) further configured to convert the quadrature signal to a one-bit quadrature digital signal; and

an interface circuit coupled to provide the one-bit in-phase digital signal and the one-bit quadrature digital signal to a digital down-converter circuit.

2. The radio-frequency (RF) apparatus of claim 1, further comprising:

a second integrated circuit coupled to the first integrated circuit, the second integrated circuit comprising;

a local oscillator configured to generate the local oscillator signal.

3. The radio-frequency (RF) apparatus of claim 1, wherein the low-noise amplifier (LNA) comprises tri-band low-noise amplifier circuitry.

4. The radio-frequency (RF) apparatus of claim 3, further comprising a filter coupled to the low-noise amplifier.

5. The radio-frequency (RF) apparatus of claim 4, further comprising antenna interface circuitry coupled to the filter.

6. The radio-frequency (RF) apparatus of claim 5, further comprising an antenna coupled to the antenna interface circuitry.

7. A method of processing signals in an integrated circuit configured to receive radio-frequency (RF) signals, the method comprising:

receiving a radio-frequency (RF) signal;

amplifying the radio-frequency signal (RF) to provide an amplified radio-frequency (RF) signal;

down-converting the amplified radio-frequency (RF) signal to generate an in-phase signal and a quadrature signal;

programmably amplifying the in-phase signal to generate an amplified in-phase signal;

programmably amplifying the quadrature signal to generate an amplified quadrature signal;

converting the amplified in-phase and quadrature signals to one-bit in-phase and quadrature digital signals, respectively; and

communicating, via a one-bit digital interface, the one-bit in-phase and quadrature digital signals to a digital down-converter circuit.

8. The method of claim 7, wherein down-converting the amplified radio-frequency (RF) signal to generate an in-phase signal and a quadrature signal further comprises mixing the amplified radio-frequency signal with a local-oscillator signal in order to generate the in-phase and quadrature signals.

9. The method of claim 8, wherein converting the amplified in-phase and quadrature signals to one-bit in-phase and quadrature digital signals further comprises using sigma-delta converter circuitry.

10. The method of claim 9, wherein the one-bit in-phase digital signal comprises a differential signal.

11. The method of claim 10, wherein the one-bit quadrature digital signal comprises a differential signal.

12. The method of claim 11, wherein the local oscillator signal comprises a differential radio-frequency local-oscillator signal.