Association of host translations that are associated to an access control level on a PCI bridge that supports virtualization

• US 7,941,577 B2
• Filed: 06/13/2008
• Issued: 05/10/2011
• Est. Priority Date: 02/25/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kiel, Harvey G., Buckland, Patrick A., Recio, Renato J., Srikrishnan, Jaya, Arndt, Richard L.
• Primary Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US12/139,063
• Publication Number:
  US 20080270735A1
• Time in Patent Office: 1,061 Days
• Field of Search: 710/1, 710 8- 10, 710/34, 710/36, 710/37, 710/313, 711/1, 711/141, 711/200
• US Class Current: 710/37
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

A method, computer program product, and distributed data processing system that allows a system image within a multiple system image virtual server to directly expose a portion, or all, of its associated system memory to a shared PCI adapter without having to go through a trusted component, such as a Hypervisor. Specifically, the present invention is directed to a mechanism for sharing conventional PCI I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications.

Claims

1. A data processing system for performing a record operation, wherein the record operation allows a system image to record its memory addresses with a super-privileged resource, comprising:

a bus system;

a system image, which utilizes the bus system; and

a hypervisor that utilizes the bus system, wherein the hypervisor receives a memory record request from the system image;

translates a first memory address used by the system image into a second memory address used by one of a system processor and system input/output chips to access memory;

locates a memory record entry in one of a plurality of address translation and protection tables used by the one of a system processor and system input/output chips to access host memory in response to determining that the second memory address is associated with the system image that issued the memory record request;

creates a peripheral component interconnect bus address associated with the second memory address;

records into the memory record entry of the one of the plurality of address translation and protection tables a memory translation required to convert the peripheral component interconnect bus address into the second memory address;

records into the memory record entry of the one of the plurality of address translation and protection tables a bus number, device number, and function number associated with one of a plurality of peripheral component interconnect bus adapters that is associated with the peripheral component interconnect bus address and second memory address;

returns the peripheral component interconnect bus address to the system image that issued the memory record request in response to determining that the record operation is successful;

creates an indirect address translation and protection table that includes a plurality of entries, each one of the plurality of entries being referenced by a bus number, device number, and function number associated with one of the plurality of peripheral component interconnect bus adapters;

includes, in each one of the plurality of entries in the indirect address translation and protection table, a pointer to one of the plurality of address translation and protection tables;

receives an operation from a particular one of the plurality of peripheral component interconnect bus adapters;

uses a bus number, device number, and function number associated with the particular one of the plurality of peripheral component interconnect bus adapters to locate a particular entry in the indirect address translation and protection table; and

uses a particular pointer that is included in the located particular entry to identify a particular one of the plurality of address translation and protection tables.

2. A computer program product, which is stored in a computer readable medium, for performing a record operation, wherein the record operation allows a system image to record its memory addresses with a super-privileged resource, the method comprising:

first instructions for receiving a memory record request from the system image;

second instructions for translating a first memory address used by the system image into a second memory address used by one of a system processor and system input/output chips to access memory;

third instructions for locating a memory record entry in one of a plurality of address translation and protection tables used by the one of a system processor and system input/output chips to access host memory in response to determining that the second memory address is associated with the system image that issued the memory record request;

fourth instructions for creating a peripheral component interconnect bus address associated with the second memory address;

fifth instructions for recording into the memory record entry of the one of the plurality of address translation and protection tables a memory translation required to convert the peripheral component interconnect bus address into the second memory address;

sixth instructions for recording into the memory record entry of the one of the plurality of address translation and protection tables a bus number, device number, and function number associated with one of a plurality of peripheral component interconnect bus adapters that is associated with the peripheral component interconnect bus address and second memory address;

seventh instructions for returning the peripheral component interconnect bus address to the system image that issued the memory record request in response to determining that the record operation is successful;

eighth instructions for creating an indirect address translation and protection table that includes a plurality of entries, each one of the plurality of entries being referenced by a bus number, device number, and function number associated with one of the plurality of peripheral component interconnect bus adapters;

ninth instructions for including, in each one of the plurality of entries in the indirect address translation and protection table, a pointer to one of the plurality of address translation and protection tables;

tenth instructions for receiving an operation from a particular one of the plurality of peripheral component interconnect bus adapters;

eleventh instructions for using a bus number, device number, and function number associated with the particular one of the plurality of peripheral component interconnect bus adapters to locate a particular entry in the indirect address translation and protection table; and

eighth instructions for using a particular pointer that is included in the located particular entry to identify a particular one of the plurality of address translation and protection tables.