Methods and systems for a memory section

• US 7,941,595 B2
• Filed: 05/15/2007
• Issued: 05/10/2011
• Est. Priority Date: 10/31/2002
• Status: Expired due to Fees

• Current Assignee: RPX Corporation
• Original Assignee: Ring Technology Enterprises of Texas LLC (IPNav)
• Inventors: Bullen, Melvin James, Lynch, William Thomas, Dodd, Steven Louis, Herbison, David James
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Faal; Baboucarr
• Application Number:
  US11/798,573
• Publication Number:
  US 20080052454A1
• Time in Patent Office: 1,456 Days
• Field of Search: None
• US Class Current: 711/109
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Claims

1. A storage hub comprising:

a memory section including at least one memory device;

a switch comprising a configurable switching fabric configured to form a connection between the memory section and a device external to the storage hub, wherein the switch directs data transferring between the memory section and the device across the connection according to destination information in the directed data, wherein the destination information specifies the device; and

a management complex, communicatively connected to the switch, comprising a processor that configures the switch,

wherein the memory section further includes one or more shift registers interconnected in series including;

one or more shift registers interconnected in series that write data to the memory device; and

one or more shift registers interconnected in series that read data from the memory device, wherein data loaded into the shift registers are shifted from one of the shift registers to a next one of the shift registers according to a clock signal, such that the shift registers maintain their shift frequency during any loading of the data between the shift registers and the memory device.

2. The storage hub of claim 1, further comprising:

a non-volatile storage device, connected to the switch, that stores a copy of the data transferring between the memory section and the device.

3. The storage hub of claim 1, wherein the management complex configures the switch by downloading to the switch an algorithm for switching data based on the destination information in the directed data.

4. The storage hub of claim 1, wherein the switch further comprises:

a processor that receives a communication from the management complex and configures the connection in the configurable switching fabric in response to the communication.

5. The storage hub of claim 4, wherein the processor receives a read address for data to be transferred from the memory section to the device, substitutes a new address for the read address, and forwards the new address to the memory section, causing data to be read from the memory section according to the new address.

6. The storage hub of claim 4, wherein the memory section includes the destination information with the data being transferred from the memory section to the device;

and wherein the processor recognizes the destination information among the data and configures the switch fabric to form the connection between the memory section and the device specified by the recognized destination information.