RISC microprocessor architecture implementing multiple typed register sets

• US 7,941,636 B2
• Filed: 12/31/2009
• Issued: 05/10/2011
• Est. Priority Date: 07/08/1991
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Nguyen, Le Trong, Chen, Sho Long, Garg, Sanjiv, Lentz, Derek J.
• Primary Examiner(s): DONAGHUE, LARRY D
• Application Number:
  US12/650,998
• Publication Number:
  US 20100106942A1
• Time in Patent Office: 495 Days
• Field of Search: 712/23, 712/228
• US Class Current: 712/23
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register file is configured to store operands defined by the one or more fields and is configured to store results of execution of the instructions in a destination defined by the one or more fields. The register file includes (i) a first register set having a register configured to store data of a single data type and (ii) a second register set having a register configured to store data of a plurality of data types. The register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.

Claims

1. An apparatus, comprising:

an execution unit configured to execute instructions including one or more fields; and

a register file configured to store operands defined by the one or more fields and configured to store results of execution of the instructions in a destination defined by the one or more fields,

wherein the register file includes;

a first register set having a register configured to store data of a single data type; and

a second register set having a register configured to store data of a plurality of data types, and

wherein the register file is responsive to the one or more fields in at least one of the instructions to retrieve an operand of the at least one of the instructions from, or to store a result of the at least one of the instructions into, one of the registers of the first register set or the second register set as defined by the one or more fields of the at least one of the instructions.

2. The apparatus of claim 1, wherein:

the first register set comprises a first subset of registers, a second subset of registers, and a shadow set of registers,

the shadow set of registers has a same number of registers as a number of registers in the second subset of registers, and

in a first operating mode each operand access to the second subset of registers is directed to the second subset of registers, and in a second operating mode each operand access to the second subset of registers is directed to the shadow set of registers.

3. The apparatus of claim 2, wherein each operand access to the first subset of registers is directed to the first subset of registers.

4. The apparatus of claim 1, wherein each register in the first register set is configured to store an integer value and each register in the second register set is configured to store an integer value or a floating point value.

5. The apparatus of claim 1, wherein one register of the first register set is dedicated to the value zero (0), and one register in the second register set is dedicated to the value zero (0).

6. The apparatus of claim 1, wherein the register file further comprises a third register set comprising a plurality of registers, each of which is configured to store a Boolean value.

7. A method for executing an instruction in an instruction execution unit, comprising:

decoding the instruction having one or more fields;

accessing a register file, wherein the register file includes first and second register sets that store operands defined by the one or more fields and that store results of execution of the instruction in a destination defined by the one or more fields,

wherein the first register set stores data of a first data type, and

wherein the second register set stores data of the first data type or data of a second data type;

retrieving an operand of the instruction from one of the plurality of registers in one of the plurality of register sets as defined by the one or more fields; and

storing a result of the execution of the instruction into one of the plurality of registers in one of the plurality of register sets as defined by the one or more fields.

8. The method of claim 7, further comprising:

using a first subset of registers, a second subset of registers, and a shadow set of registers as a first register set, wherein the shadow subset of registers has a same number of registers as a number of registers in the second subset of registers;

in a first operating mode, directing each operand access to the second subset of registers to the second subset of registers; and

in a second operating mode, directing each operand access to the second subset of registers to the shadow subset of registers.

9. The method of claim 8, further comprising:

directing each access to the first subset of registers to the first subset of registers.

10. The method of claim 7, wherein the first data type is integer data and the second data type is floating point data.

11. The method of claim 7, further comprising:

dedicating a register of the first register set to a permanent value of zero (0); and

dedicating a register of the second register set to a permanent value of zero (0).

12. The method of claim 7, further comprising:

including a third register set in the register file, the third register set comprising a plurality of registers, at least one of which is configured to store a Boolean value.