Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination

• US 7,941,647 B2
• Filed: 10/31/2007
• Issued: 05/10/2011
• Est. Priority Date: 01/28/1999
• Status: Expired due to Fees

• Current Assignee: Advanced Silicon Technologies LLC
• Original Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Inventors: Yates, Jr., John S., Reese, David L., Van Dyke, Korbin S., Ramesh, T. R., Hohensee, Paul H.
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US11/982,419
• Publication Number:
  US 20090204785A1
• Time in Patent Office: 1,287 Days
• Field of Search: None
• US Class Current: 712/220
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/30196 using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeline, the memory being divided into pages for management by a virtual memory manager, a single address space of the memory having first and second pages. A memory unit fetches instructions from the memory for execution by the pipeline, and fetches stored indicator elements associated with respective memory pages of the single address space from which the instructions are to be fetched. Each indicator element is designed to store an indication of which of two different computer architectures and/or execution conventions under which instruction data of the associated page are to be executed by the processor pipeline. The memory unit and/or processor pipeline recognizes an execution flow from the first page, whose associated indicator element indicates the first architecture or execution convention, to the second page, whose associated indicator element indicates the first architecture or execution convention. In response to the recognizing, a processing mode of the processor pipeline or a storage content of the memory adapts to effect execution of instructions in the architecture and/or under the convention indicated by the indicator element corresponding to the instruction'"'"'s page.

Claims

1. A method, comprising:

decoding a macroinstruction of a computer, the decoding generating a plurality of iterations of a sequence of one or more microinstructions, including;

a pattern of microinstructions implementing a basic operation, and

a branch instruction predicted not taken;

on detecting that an iteration completes operation of the macroinstruction, adding a marker indicating an end of the macroinstruction to a microinstruction in a pipeline downstream of an instruction decoder;

after reaching a termination condition of the macroinstruction, partially executing an iteration beyond the termination, the partial execution committing at least one side-effect to an architecturally-visible resource of the computer, and raising an exception to transfer control to a second microinstruction stream; and

in the second microinstruction stream, unwinding the side-effects committed by the post-termination iteration.

2. A method, comprising:

decoding a macroinstruction of a computer, the decoding generating a plurality of iterations of;

a pattern of microinstructions implementing a basic operation, wherein the microinstruction set is architecturally exposed to programs fetched from an architecturally-visible memory of the computer, and

a branch instruction predicted not taken.

3. The method of claim 2, further comprising:

on detecting that an iteration completes operation of the macroinstruction, adding a marker indicating an end of the macroinstruction to a microinstruction in a pipeline downstream of an instruction decoder.

4. The method of claim 2, further comprising:

partially executing an iteration beyond a termination condition of a loop of a decoded microinstruction stream, the partial execution committing at least one side-effect to an architecturally-visible resource of the computer;

raising an exception to transfer control to a second microinstruction stream; and

in the second microinstruction stream, unwinding the side-effects committed by the post-termination iteration.

5. The method of claim 2, wherein instructions of the microinstruction set are managed by a memory management unit between a main memory of the computer and one or more cache levels.

6. The method of claim 2, wherein the branch microinstruction is generated including a marker indicating that the branch microinstruction defines a boundary between two successive iterations.

7. A computer, comprising:

an instruction decoder designed to decode macroinstructions into microinstructions for execution in an instruction pipeline on a computer, and for at least one macroinstruction that includes internal iterations, the decoding of the internal-iteration macroinstruction designed to generate a plurality of iterations of;

a pattern of microinstructions for implementing a basic operation of an internal iteration of the internal-iteration macroinstruction, and

a branch microinstruction predicted not taken, wherein the branch microinstruction is generated including a marker indicating that the branch microinstruction defines a boundary between two successive iterations of the internal-iteration macroinstruction;

the instruction decoder being further designed to cease generating iterations on detection of a branch mispredict.

8. The computer of claim 7, further comprising:

instruction fetch and execution circuitry designed to fetch and execute instructions in both the macroinstruction set and the microinstruction set, each of the instruction sets including store instructions to write data to a memory of the computer;

store monitoring circuitry designed to monitor the store instructions and to invalidate any copies of a datum in memory overwritten by the store instructions, including copies of instructions in any instruction cache in the instruction set other than the instruction set of the current store instruction.

9. The computer of claim 7, further comprising:

execution circuitry designed to execute an instruction calling for waiting to allow a pipeline to drain and to set bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

10. The computer of claim 7, wherein the branch microinstruction is a branch instruction available to a program to be fetched from a memory of the computer.

11. A method, comprising:

decoding a macroinstruction on a computer, the macroinstruction calling for a plurality of iterations of a sequence of one or more microinstructions; and

on detecting that an iteration completes operation of the macroinstruction, adding a marker indicating an end of the macroinstruction to a microinstruction in a pipeline downstream of an instruction decoder.

12. The method of claim 11, further comprising:

after reaching a termination condition of the iterations, partially executing an iteration beyond the termination, the partial execution committing at least one side-effect to an architecturally-visible resource of the computer, and raising an exception to transfer control to a second microinstruction stream;

in the second microinstruction stream, unwinding the side-effects committed by the post-termination iteration.

13. The method of claim 11, further comprising:

executing a microinstruction on the computer, the microinstruction storing into a memory location a value of a second instruction coded in the macroinstruction set;

in response to the storing, clearing a memory system, including an instruction cache, and execution pipeline of the computer of the former content of the memory location;

executing the second instruction in the execution pipeline.

14. The method of claim 11, wherein the detecting includes detecting a branch mispredict.

15. The method of claim 14, wherein the mispredict is detected on a branch microinstruction architecturally available to a program fetched from a memory of the computer.

16. The method of claim 11, wherein the branch microinstruction is generated including a marker indicating that the branch microinstruction defines a boundary between two successive iterations.

17. A computer, comprising:

an instruction decoder designed to decode a macroinstruction set that includes a macroinstruction calling for a plurality of iterations of a sequence of one or more microinstructions;

a pipeline stage downstream of the instruction decoder designed to detect that operation of the macroinstruction is complete, and in response, to add a marker to a microinstruction indicating an end of the macroinstruction.

18. The computer of claim 17:

wherein the decoder, when decoding the macroinstruction, is designed to generate a plurality of iterations of;

a pattern of microinstructions implementing a basic operation, and

a branch microinstruction predicted not taken.

19. The computer of claim 17, further comprising

circuitry designed to execute an instruction calling for waiting to allow a pipeline to drain and to set bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

20. A method, comprising:

after reaching a termination condition of a loop of a first microinstruction stream executing in a computer, the microinstruction stream being generated by decoding a macroinstruction, partially executing a loop iteration beyond the termination, the partial execution committing at least one side-effect to an architecturally-visible resource of the computer, and raising an exception to transfer control to a second microinstruction stream;

in the second microinstruction stream, unwinding the side-effects committed by the post-termination iteration.

21. The method of claim 20, further comprising:

executing a microinstruction of a computer, the microinstruction storing into a memory location a value of a second instruction coded in a second instruction set;

in response to the storing, clearing an instruction cache and execution pipeline of the computer of the former content of the memory location;

executing the second instruction in the execution pipeline.

22. The method of claim 20, further comprising:

executing an instruction that calls for waiting to allow a pipeline to drain and setting bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

23. The method of claim 20, further comprising:

ceasing to generate iterations when a termination condition of the macroinstruction is detected in an execution stage of an instruction pipeline of the computer.

24. The method of claim 23, wherein the detection of the termination condition includes detecting a branch mispredict.

25. The method of claim 20, wherein each iteration completes with a branch microinstruction architecturally available to a program fetched from a memory of the computer.

26. The method of claim 25, wherein the branch microinstruction is generated including a marker indicating that the branch microinstruction defines a boundary between two successive iterations.

27. A computer, comprising:

circuitry designed to partially execute a post-termination iteration of a loop of a first microinstruction stream executing in the computer, the partial execution designed to commit at least one side-effect to an architecturally-visible resource of the computer, and to raise an exception to transfer control to a second microinstruction stream;

software of the second microinstruction stream, programmed to unwind side-effects committed by the post-termination iteration.

28. The computer of claim 27, further comprising:

an instruction decoder designed to decode macroinstructions into microinstructions for execution in an instruction pipeline on the computer, and for at least one macroinstruction, the decoding generating a plurality of iterations of;

a pattern of microinstructions implementing a basic operation, and

a branch microinstruction predicted not taken.

29. The computer of claim 27, further comprising:

a pipeline stage downstream of an issue buffer of the computer, designed to detect the termination condition of the loop, and in response, to add a marker to a microinstruction indicating an end of the macroinstruction.

30. The computer of claim 27, wherein the loop of the first microinstruction stream includes instructions generated by decoding a single macroinstruction fetched from memory of the computer.

31. The computer of claim 27, wherein an instruction generator of the computer joins iterations of the loop by branches predicted not taken.

32. A method comprising:

in a computer having instruction fetch circuitry for fetching instructions in first and second instruction sets from a memory of the computer and executing the instructions, executing a first instruction coded in the first instruction set, the first instruction storing into a memory location a value of a second instruction coded in the second instruction set,

in response to the storing, clearing an instruction cache and execution pipeline of the computer of the former content of the memory location;

executing the second instruction in the execution pipeline.

33. The method of claim 32, further comprising:

decoding an instruction of the second instruction set, the decoding generating a plurality of iterations of;

a pattern of instructions of the first instruction set implementing a basic operation, and

a branch instruction of the first instruction predicted not taken.

34. The method of claim 32, further comprising:

executing an instruction calling for waiting to allow a floating-point pipeline of the computer to drain and to set bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

35. The method of claim 32, wherein an instruction decoder for the second instruction set designed to generate instructions in the first instruction set for execution in the execution pipeline.

36. The method of claim 32, wherein the instructions in the execution pipeline are not tagged with an indication of an instruction set of origin.

37. The method of claim 32, wherein the monitoring is based on comparing addresses in a physical address space.

38. A computer, comprising:

instruction fetch and execution circuitry designed to fetch and execute instructions in two different instruction sets, each instruction set including store instructions to write data to a memory of the computer;

store monitoring circuitry designed to monitor the store instructions and to invalidate any copies of a datum overwritten by the store instructions, including copies of instructions in any instruction cache, in the instruction set other than the instruction set of the current store instruction.

39. The computer of claim 38, further comprising:

an instruction decoder designed to decode an instruction in a first of the instruction sets, and in response, to generate a plurality of iterations of a sequence of one or more instructions in a second one of the instruction sets;

a pipeline stage downstream of the instruction decoder designed to detect that operation of the decoded instruction is complete, and in response, to add a marker to one of the generated instructions indicating an end of the macroinstruction.

40. The computer of claim 38:

wherein the instruction fetch and execute circuitry is further designed to partially execute a post-termination iteration of a loop within a first instruction in a first one of the instruction sets, the partial execution to commit at least one side-effect to an architecturally-visible resource of the computer, and to raise an exception to transfer control to a second instruction stream in a second one of the instruction sets, programmed to unwind side-effects committed by the post-termination iteration.

41. A method, comprising:

decoding and executing an instruction on a computer, execution of the instruction including waiting to allow a pipeline to drain, and setting bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

42. The method of claim 41, wherein instruction fetch and execution circuitry of the computer are designed to fetch and execute a macroinstruction set and a microinstruction set from memory.

43. The method of claim 42, further comprising:

decoding a macroinstruction of the computer, the decoding generating a plurality of iterations of;

a pattern of microinstructions implementing a basic operation, and

a branch instruction predicted not taken.

44. The method of claim 42, further comprising:

decoding a macroinstruction on the computer, the macroinstruction calling for a plurality of iterations of a sequence of one or more microinstructions; and

on detecting that an iteration completes operation of the macroinstruction, adding a marker indicating an end of the macroinstruction to a microinstruction in the pipeline downstream of the instruction decoder.

45. The method of claim 42, further comprising:

emitting the instruction as a microinstruction in response to a macroinstruction whose execution is dependent on a full/empty state of a floating-point top-of-stack.

46. A computer, comprising:

execution circuitry designed to execute an instruction calling for waiting to allow a pipeline to drain and to set bits of a floating-point control word to values denoted in an explicit immediate field of the instruction.

47. The computer of claim 46, further comprising:

instruction fetch and execution circuitry of the computer are designed to fetch and execute instructions in two different instruction sets.

48. The computer of claim 46, further comprising:

each instruction set including instructions defined to write data to a memory of the computer;

store monitoring circuitry designed to monitor the data write instructions and to invalidate any copies of a datum in memory overwritten by the data write instructions, including copies of instructions in the instruction set other than the instruction set of the current data write instruction.

49. The computer of claim 46, wherein the instruction specifying individual bits of the floating-point control word to be written, in addition to values to be written to those bits.

50. The computer of claim 46, wherein

the execution circuitry is further designed to execute an instruction calling for waiting to allow a pipeline to drain and to raise an exception based on a test of bits of a floating-point control word.

51. A computer, comprising:

an instruction decoder designed to decode macroinstructions into microinstructions for execution in an instruction pipeline on the computer, and for at least one macroinstruction, the decoder designed to generate a plurality of iterations of a pattern of microinstructions implementing a basic operation of the macroinstruction, a microinstruction of each of the plurality of iterations including a marker indicating that the marked microinstruction defines a boundary between two successive iterations, the microinstruction set being architecturally exposed for execution from an architecturally-exposed memory; and

operand commit circuitry designed to detect the marker, and in response, to commit results of an iteration to architectural state of the computer.

52. The computer of claim 51, further comprising:

a pipeline stage downstream of the instruction decoder designed to detect that operation of the macroinstruction is complete, and in response, to add a marker to a microinstruction indicating an end of the macroinstruction.

53. The computer of claim 51, wherein:

the microinstruction to be generated including the iteration boundary marker is a branch microinstruction predicted not taken.

54. The computer of claim 51, further comprising:

circuitry designed to partially execute a post-termination iteration of a loop of a first microinstruction stream executing in the computer, the partial execution to commit at least one side-effect to an architecturally-visible resource of the computer, and to raise an exception to transfer control to a second microinstruction stream;

software of the second microinstruction stream, programmed to unwind side-effects committed by the post-termination iteration.