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Photolithographic process simulation in integrated circuit design and manufacturing

  • US 7,941,768 B1
  • Filed: 02/20/2007
  • Issued: 05/10/2011
  • Est. Priority Date: 01/11/2006
  • Status: Active Grant
First Claim
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1. A method for designing an integrated circuit comprising:

  • receiving a geometrical design intent for at least a portion of the integrated circuit;

    receiving at least a first value and a second value for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit;

    simulating with a processing system the photolithographic process at the first and second values for the at least one process variation using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results, wherein said first and second values were not used in generation of said one or more models; and

    in response to said simulation results, re-routing a portion of the geometrical design intent so as to improve manufacturability of the integrated circuit.

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