Photolithographic process simulation in integrated circuit design and manufacturing

• US 7,941,768 B1
• Filed: 02/20/2007
• Issued: 05/10/2011
• Est. Priority Date: 01/11/2006
• Status: Active Grant

• Current Assignee: Olambda Incorporated
• Original Assignee: Olambda Incorporated
• Inventors: Wei, Haiqing
• Primary Examiner(s): Lin; Sun J
• Application Number:
  US11/708,299
• Time in Patent Office: 1,540 Days
• Field of Search: 716/13, 716/21, 716/5, 716/19, 716/50, 716/54, 716/102, 716/106, 716/130
• US Class Current: 716/54
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions

Abstract

A method, system, and related computer program products for computer simulation of a photolithographic process is described. In one embodiment, a method for designing an integrated circuit is provided. The geometrical design intent and process condition values are received for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit. The photolithographic process is simulated at the process condition values using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results.

Claims

1. A method for designing an integrated circuit comprising:

receiving a geometrical design intent for at least a portion of the integrated circuit;

receiving at least a first value and a second value for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit;

simulating with a processing system the photolithographic process at the first and second values for the at least one process variation using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results, wherein said first and second values were not used in generation of said one or more models; and

in response to said simulation results, re-routing a portion of the geometrical design intent so as to improve manufacturability of the integrated circuit.

2. The method of claim 1, further comprising receiving at least a third value and a fourth value for a second process variation associated with the photolithographic process.

3. The method of claim 1, wherein said at least one process variation is selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

4. The method of claim 1, wherein said step of simulating comprises simulating the photolithographic process using the one or more models over a substantially large physical area of said integrated circuit.

5. The method of claim 4, wherein said step of simulating further comprises simulating the photolithographic process using the one or more models over an area in which a ratio of the area over square of a critical dimension of the geometrical design intent is at least 10⁶.

6. The method of claim 5, wherein said step of simulating further comprises simulating the photolithographic process using the one or more models over an area in which a ratio of the area over a square of a critical dimension of the geometrical design intent is at least 10⁸.

7. The method of claim 6, wherein said step of simulating further comprises simulating the photolithographic process using the one or more models over substantially the entire area of the integrated circuit.

8. The method of claim 1, further comprising a step of estimating a value for yield of the integrated circuit based at least in part on the simulation results.

9. The method of claim 8, wherein said step of re-routing is in part in response to the outcome of said step of estimating a value for yield.

10. The method of claim 1, further comprising a step of identifying one or more locations on the geometrical design intent associated with potential failures based on the simulation results.

11. The method of claim 1, wherein said step of receiving comprises receiving a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, and wherein said step of simulating comprises simulating the photolithographic process at each process condition, the method further comprises steps of:

receiving one or more design constraints to aid in determining if the geometrical design intent will lead to a functioning integrated circuit; and

estimating, for each process condition whether design constraints will have been satisfied based upon the simulation results.

12. The method of claim 11, further comprising a step of determining a boundary between passing and failing the design constraints within space of the process variations.

13. The method of claim 12, further comprising a step of displaying the boundary to the user.

14. The method of claim 11, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one location on the geometrical design intent related to the failure to satisfy.

15. The method of claim 11, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one type of wafer pattern related to the failure to satisfy.

16. The method of claim 11, wherein said step of re-routing is in part in response to an outcome of said step of estimating.

17. A computer program product on a computer readable medium comprising computer code that, when executed on a computing device, provides a capability of designing an integrated circuit according to the method of claim 1.

18. A system for designing an integrated circuit comprising:

a computer input/output system adapted to receive a geometrical design intent for at least a portion of the integrated circuit, and receive at least a first value and a second value for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit;

a processor configured and programmed to simulate the photolithographic process at the first and second values for the at least one process variation using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results, wherein said first and second values were not used in generation of said one or more models; and

a computer system for re-routing a portion of the geometrical design intent so as to improve manufacturability of the integrated circuit.

19. The system as in claim 18, wherein the computer system for re-routing is adapted to receive input guidance from a user.

20. The system as in claim 18, wherein said at least one process variation is selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

21. The system of claim 18, wherein said processor is further configured and programmed to simulate the photolithographic process using the one or more models over a substantially large physical area of said integrated circuit.

22. The system of claim 21, wherein a ratio of an area over square of a critical dimension of the geometrical design intent is at least 10⁶.

23. The system of claim 22, wherein said processor is further configured and programmed to simulate the photolithographic process over substantially the entire area of the integrated circuit.

24. The system of claim 21, wherein a ratio of an area over square of a critical dimension of the geometrical design intent is at least 10⁸.

25. The system of claim 18, wherein said processor is further configured and programmed to estimate a value for yield of the integrated circuit based at least in part on the simulation results.

26. The system of claim 25, wherein the re-routing is in part performed in response to an outcome of said action of estimating a value for yield.

27. The system of claim 18, wherein said processor is further configured and programmed to identify one or more locations on the geometrical design intent associated with potential failures based on the simulation results.

28. The system of claim 18, wherein said computer input/output system is further adapted to receive a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, and to receive one or more design constraints to aid in determining if the geometrical design intent will lead to a functioning integrated circuit, and wherein said processor is further configured and programmed to simulate the photolithographic process at each process condition, and to estimate, for each process condition, whether the design constraints will have been satisfied based upon the simulation results.

29. The system of claim 28, wherein said processor is further configured and programmed to determine a boundary between passing and failing the design constraints within space of the process variations.

30. The system of claim 29, further comprising a display system adapted to display the boundary to a user.

31. The system of claim 28, wherein the processor is further configured and programmed to identify for at least one condition under which the design constraints are not satisfied, at least one location on the design related to the failure to satisfy.

32. The system of claim 28, wherein the re-routing is in part performed in response to an outcome of said action of estimating.

33. A method for designing an integrated circuit comprising:

receiving a geometrical design intent for at least a portion of the integrated circuit;

receiving at least a first value and a second value for at least one process variation associated with a photolithographic process to be used in fabricating the integrated circuit;

simulating with a processing system the photolithographic process using one or more models characterizing the photolithographic process and the geometrical design intent to generate simulation results;

estimating a quantitative value for yield of the integrated circuit based at least in part on the simulation results; and

in response to said simulation results, re-routing a portion of the geometrical design intent so as to improve manufacturability of the integrated circuit.

34. The method of claim 33, wherein said at least one process variation is selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

35. The method of claim 33, wherein said step of simulating comprises simulating the photolithographic process using the one or more models over a substantially large physical area of said integrated circuit.

36. The method of claim 35, wherein said step of simulating further comprises simulating the photolithographic process using the one or more models over an area in which a ratio of the area over square of a critical dimension of the geometrical design intent is at least 10⁸.

37. The method of claim 36, wherein said step of simulating further comprises simulating the photolithographic process using the one or more models over substantially the entire area of the integrated circuit.

38. The method of claim 33, further comprising a step of identifying one or more locations on the geometrical design intent associated with potential failures based on the simulation results.

39. The method of claim 33, wherein said step of receiving comprises receiving a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, and wherein said step of simulating comprises simulating the photolithographic process at each process condition, the method further comprises the steps of:

receiving one or more design constraints to aid in determining if the geometrical design intent will lead to a functioning integrated circuit; and

estimating, for each process condition whether design constraints will have been satisfied based upon the simulation results.

40. The method of claim 39, further comprising a step of determining a boundary between passing and failing the design constraints within space of the process variations.

41. The method of claim 39, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one location on the geometrical design intent related to the failure to satisfy.

42. The method of claim 33, wherein said step of re-routing is in part in response to an outcome of said step of estimating a value for yield.

43. A method for simulating a photolithographic process of a design onto a target comprising:

simulating with a processing system the photolithographic process over a substantially large physical area of the target for a plurality of values of at least one process variation associated with the photolithographic process, wherein the at least one process variation is neither dose/exposure nor focus/defocus;

receiving a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, wherein said step of simulating includes simulating for each of the plurality of process conditions;

receiving one or more design constraints to aid in determining if the design will lead to a functioning integrated circuit; and

estimating, for each process condition whether the design constraints will have been satisfied based upon simulation results generated by said step of simulating.

44. The method of claim 43, wherein said step of simulating comprises simulating the photolithographic process at a plurality of depths within the target.

45. The method of claim 43, wherein said step of simulating comprises simulating the photolithographic process on a plurality of portions of the target, the method further comprising a step of combining results of said simulations on said plurality of portions of the target.

46. The method of claim 43, wherein said at least one process variation is selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

47. The method of claim 43 wherein said step of simulating further comprises simulating the photolithographic process over an area on the target in which a ratio of the area over square of a critical dimension of the design is at least 10⁶.

48. The method of claim 47 wherein said step of simulating further comprises simulating the photolithographic process over an area on the target in which a ratio of the area over square of a critical dimension of the design is at least 10⁸.

49. The method of claim 48, wherein said step of simulating further comprises simulating the photolithographic process over substantially the entire design.

50. The method of claim 43, further comprising a step of estimating a value for yield of the design based at least in part on results of said step of simulating.

51. The method of claim 43, wherein the design is a geometrical design intent.

52. The method of claim 43, wherein the design is a mask layout.

53. The method of claim 43, further comprising a step of determining a boundary between passing and failing the design constraints within space of the process variations.

54. The method of claim 53, further comprising a step of displaying the boundary to the user.

55. The method of claim 43, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one location on the design related to the failure to satisfy.

56. The method of claim 43, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one type of wafer pattern related to the failure to satisfy.

57. The method of claim 43, further comprising a step of altering a mask used in the photolithographic process based at least in part on said step of estimating, and so as to improve manufacturability of the mask.

58. The method of claim 43, further comprising a step of changing parameters of equipment used in the photolithographic process in response to said step of estimating.

59. The method of claim 58, further comprising a step of altering the design of at least some part of the equipment based in part on results of said step of estimating.

60. The method of claim 43 wherein the design is a test pattern.

61. A computer program product on a computer readable medium comprising computer code that, when executed on a computing device, simulates a photolithographic process in according to the method of claim 43.

62. A system for simulating a photolithographic process comprising:

a computer input/output system adapted and configured to receive a design and a plurality of process conditions, each process condition comprising a value for each of a plurality of process variations associated with the photolithographic process, wherein at least one of said process conditions is neither dose/exposure nor focus/defocus; and

a processor configured and programmed to simulate the photolithographic process over a substantially large physical area of a target of the design at each of the plurality of process conditions, wherein the computer input/output system is further adapted to receive one or more design constraints to aid in determining if the design will lead to a functioning integrated circuit, and the processor is further configured and programmed to estimate for each process condition whether the design constraints will have been satisfied based upon simulation results generated by simulating the photolithographic process.

63. The system of claim 62, wherein said processor is further configured and programmed to simulate the photolithographic process at a plurality of depths within the target.

64. The system of claim 62, wherein said processor is further configured and programmed to simulate the photolithographic process on a plurality of portions of the target, and to combine results of simulations on said plurality of portions of the target.

65. The system of claim 62, wherein the plurality of process variations is selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

66. The system of claim 62 wherein a ratio of substantially large physical area over square of a critical dimension of the design is at least 10⁶.

67. The system of claim 62 wherein a ratio of substantially large physical area over square of a critical dimension of the design is at least 10⁸.

68. The system of claim 67, wherein a simulation takes place over substantially the entire design.

69. The system of claim 62, where the processor is further configured and programmed to estimate a value for yield of the design based at least in part on results of a simulation.

70. The system of claim 62, wherein the processor is further configured and programmed to determine a boundary between passing and failing the design constraints within a space of the process variations.

71. The system of claim 70, further comprising a display system adapted to display the boundary to a user.

72. The system of claim 62, wherein the processor is further configured and programmed to identify for at least one condition under which the design constraints are not satisfied, at least one location on the design related to the failure to satisfy.

73. The system of claim 62, wherein the processor is further configured and programmed to alter a mask used in the photolithographic process based at least in part on estimation for each process condition whether the design constraints will have been satisfied so as to improve manufacturability of the mask.

74. A method for simulating a photolithographic process of a design onto a target comprising:

simulating with a processing system the photolithographic process over a substantially large area on the target and at a plurality of depths within said target;

receiving a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, wherein said step of simulating includes simulating for each of the plurality of process conditions;

receiving one or more design constraints to aid in determining if the design will lead to a functioning integrated circuit; and

estimating, for each process condition, whether said design constraints will have been satisfied based upon simulation results.

75. The method of claim 74, wherein the design is a geometrical design intent.

76. The method of claim 74, wherein the design is a mask layout.

77. The method of claim 74, further comprising a step of determining a boundary between passing and failing the design constraints within space of the process variations.

78. The method of claim 77, further comprising a step of displaying the boundary to the user.

79. The method of claim 74, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one location on the design related to the failure to satisfy.

80. The method of claim 74, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one type of wafer pattern related to the failure to satisfy.

81. The method of claim 74, further comprising a step of altering a mask used in the photolithographic process based at least in part on said step of estimating, and so as to improve manufacturability of the mask.

82. The method of claim 74, further comprising a step of changing a parameters of equipment used in the photolithographic process in response to said step of estimating.

83. The method of claim 74, further comprising a step of altering the design of at least some part of the equipment based in part on results of said step of estimating.

84. The method of claim 74 wherein the design is a test pattern.

85. A method for simulating a photolithographic process of a design onto a target comprising:

simulating with a processing system the photolithographic process repeatedly of different portions of the design onto a plurality of different portions of the target, according to a plurality of values of at least one process variation associated with the photolithographic process, wherein the at least one process variation is neither dose/exposure nor focus/defocus;

combining results of said repeated simulations performed in said step of simulating;

receiving a plurality of process conditions, each process condition comprising a condition value for each of a plurality of process variations associated with the photolithographic process, wherein said step of simulating includes simulating for each of the plurality of process conditions;

receiving one or more design constraints to aid in determining if the design will lead to a functioning integrated circuit; and

estimating, for each process condition, whether said design constraints will have been satisfied based upon simulation results generated by said step of simulating.

86. The method of claim 85, wherein said step of simulating comprises simulating the photolithographic process at a plurality of depths within a photolithography target.

87. The method of claim 85, wherein said step of simulating is performed over a substantially large physical area.

88. The method of claim 85, wherein said the plurality of process variations are selected from a group consisting of:

exposure dose variations, intensity variations of multiple light emitters, light source chromatic variations, coherence variations, light source positioning variations, defocus variations, lens aberrations, exposure-field-dependent defocus variations and lens aberrations, immersion medium refractive index variations, immersion medium attenuation coefficient variations, stack film thickness variations, stack film material refractive index variations, stack film material attenuation coefficient variations, mask pattern errors, mask topography variations, mask material property variations, and other mask errors, photoresist optical property variations, photoresist chemical property variations, photoresist-development material variations, photoresist-development environment variations, photoresist-development process variations, etching material variations, etching environment variations, etching process variations, temperature variations, pressure variations, and processing time variations of different process steps.

89. The method of claim 85 wherein said step of simulating further comprises simulating the photolithographic process over an area on the target in which a ratio of the area over square of a critical dimension of the design is at least 10⁶.

90. The method of claim 89 wherein said step of simulating further comprises simulating the photolithographic process over an area on the target in which a ratio of the area over square of a critical dimension of the design is at least 10⁸.

91. The method of claim 90, wherein said step of simulating further comprises simulating the photolithographic process over substantially the entire area of the design.

92. The method of claim 85, further comprising a step of estimating a value for yield of the design based at least in part on results of said step of simulating.

93. The method of claim 85, further comprising a step of determining a boundary between passing and failing the design constraints within space of the process variations.

94. The method of claim 93, further comprising a step of displaying the boundary to the user.

95. The method of claim 85, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one location on the design related to the failure to satisfy.

96. The method of claim 85, further comprising a step of identifying for at least one condition under which the design constraints are not satisfied, at least one type of wafer pattern related to the failure to satisfy.

97. The method of claim 85, further comprising a step of altering a mask used in the photolithographic process based at least in part on said step of estimating, and so as to improve manufacturability of the mask.

98. The method of claim 95, further comprising a step of changing parameters of equipment used in the photolithographic process in response to said step of estimating.

99. The method of claim 98, further comprising a step of altering the design of at least some part of the equipment based in part on results of said step of estimating.

100. The method of claim 85 wherein the design is a test pattern.