SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

• US 7,943,442 B2
• Filed: 09/27/2007
• Issued: 05/17/2011
• Est. Priority Date: 01/31/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gehring, Andreas, HOENTSCHEL, JAN, Wei, Andy
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US11/862,296
• Publication Number:
  US 20080268585A1
• Time in Patent Office: 1,328 Days
• Field of Search: 438/149, 438/150, 438/151, 438/152, 438/153, 438/311, 257/E21.195
• US Class Current: 438/152
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/66128 Planar diodes
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.

Claims

1. A method, comprising:

forming a first opening and a second opening in a first device region of an SOI substrate while covering a second device region, said first and second openings extending through a buried insulating layer to a crystalline substrate material, said second device region having formed therein a first transistor and a second transistor each comprising an extension region;

forming drain and source regions in said first transistor and a first doped region in said crystalline substrate material exposed by said first opening in a common first drain/source implantation process;

forming drain and source regions in said second transistor and a second doped region in said crystalline substrate material exposed by said second opening in a common second drain/source implantation process;

forming a first spacer element on sidewalls of said first and second openings after said common first and second drain/source implantation processes and performing a further common drain/source implantation process for said first opening and said first transistor and a further common drain/source implantation process for said second opening and said second transistor; and

forming a metal silicide in said first and second transistors and said first and second doped regions.

2. The method of claim 1, further comprising annealing said drain and source regions and said first and second doped regions prior to forming said metal silicide.

3. The method of claim 1, further comprising forming a sidewall spacer on sidewalls of a gate electrode of said first and second transistors prior to forming said first and second openings.

4. The method of claim 3, further comprising removing said sidewall spacer prior to forming said metal silicide.

5. The method of claim 1, wherein said common first and second drain/source implantation processes are the final implantation processes for forming the drain and source regions of said first and second transistors.

6. The method of claim 1, wherein said spacer element in said first and second openings and sidewall spacers of gate electrodes of said first and second transistors are formed in a common process sequence.

7. The method of claim 5, further comprising forming a spacer element on sidewalls of said first and second openings prior to forming said metal silicide.

8. The method of claim 1, wherein forming said first spacer element further comprises:

forming a spacer layer in said first and second openings and over said first and second transistors; and

removing said spacer layer from above said first and second transistors, wherein a remaining portion of said spacer layer defines said first spacer element.

9. The method of claim 8, wherein forming said metal silicide further comprises forming said metal silicide in the presence of said first spacer element.

10. The method of claim 1, further comprising:

forming a second spacer element on sidewalls of said first and second openings and on sidewalls of gate electrodes of said first and second transistors prior to said common first and second drain/source implantation processes; and

performing said common first and second drain/source implantation processes in the presence of said second spacer element.

11. The method of claim 10, wherein forming said first spacer element further comprises:

forming a spacer layer in said first and second openings and over said first and second transistors in the presence of said second spacer element; and

removing said spacer layer from above said first and second transistors, wherein a remaining portion of said spacer layer defines said first spacer element.

12. The method of claim 11, further comprising removing said second spacer element from said sidewalls of said gate electrodes of said first and second transistors prior to forming said metal silicide.