SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device
First Claim
1. A method, comprising:
- forming a first opening and a second opening in a first device region of an SOI substrate while covering a second device region, said first and second openings extending through a buried insulating layer to a crystalline substrate material, said second device region having formed therein a first transistor and a second transistor each comprising an extension region;
forming drain and source regions in said first transistor and a first doped region in said crystalline substrate material exposed by said first opening in a common first drain/source implantation process;
forming drain and source regions in said second transistor and a second doped region in said crystalline substrate material exposed by said second opening in a common second drain/source implantation process;
forming a first spacer element on sidewalls of said first and second openings after said common first and second drain/source implantation processes and performing a further common drain/source implantation process for said first opening and said first transistor and a further common drain/source implantation process for said second opening and said second transistor; and
forming a metal silicide in said first and second transistors and said first and second doped regions.
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Accused Products
Abstract
A substrate diode for an SOI device is formed in accordance with an appropriately designed manufacturing flow, wherein transistor performance enhancing mechanisms may be implemented substantially without affecting the diode characteristics. In one aspect, respective openings for the substrate diode may be formed after the formation of a corresponding sidewall spacer structure used for defining the drain and source regions, thereby obtaining a significant lateral distribution of the dopants in the diode areas, which may therefore provide sufficient process margins during a subsequent silicidation sequence on the basis of a removal of the spacers in the transistor devices. In a further aspect, in addition to or alternatively, an offset spacer may be formed substantially without affecting the configuration of respective transistor devices.
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Citations
12 Claims
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1. A method, comprising:
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forming a first opening and a second opening in a first device region of an SOI substrate while covering a second device region, said first and second openings extending through a buried insulating layer to a crystalline substrate material, said second device region having formed therein a first transistor and a second transistor each comprising an extension region; forming drain and source regions in said first transistor and a first doped region in said crystalline substrate material exposed by said first opening in a common first drain/source implantation process; forming drain and source regions in said second transistor and a second doped region in said crystalline substrate material exposed by said second opening in a common second drain/source implantation process; forming a first spacer element on sidewalls of said first and second openings after said common first and second drain/source implantation processes and performing a further common drain/source implantation process for said first opening and said first transistor and a further common drain/source implantation process for said second opening and said second transistor; and forming a metal silicide in said first and second transistors and said first and second doped regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification