Asymmetric junction field effect transistor

• US 7,943,445 B2
• Filed: 02/19/2009
• Issued: 05/17/2011
• Est. Priority Date: 02/19/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Zierak, Michael J., Anderson, Frederick G., Collins, David S., Phelps, Richard A., Rassel, Robert M.
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/388,586
• Publication Number:
  US 20100207173A1
• Time in Patent Office: 817 Days
• Field of Search: 438/157, 438/193, 438/195, 438/283, 438/284, 438/286, 257/E29.264, 257/E29.268, 257/E29.279
• US Class Current: 438/157
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0843 Source or drain regions of field-effect devices
• CPC Class Codes: H01L 29/1058 with PN junction gate
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/66901 with a PN homojunction gate
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

Claims

1. A method of manufacturing a semiconductor structure comprising:

forming a stack, from bottom to top, of a lower gate region, a body layer, and an upper gate region in a semiconductor substrate comprising a semiconductor material, wherein said body layer has a doping of a first conductivity type, wherein said lower gate region and said upper gate region have a doping of a second conductivity type, and wherein said second conductivity type is the opposite of said first conductivity type;

forming an upper source region and a drain region having a doping of said first conductivity type by doping portions of said body layer with additional dopants of said first conductivity type; and

forming a lower source region having a doping of said first conductivity type by doping another portion of said body layer with additional dopants of said first conductivity type, wherein said lower source region and said upper source region constitute a source region of integral construction, and wherein a bottom surface of said upper source region abuts a top surface of said lower source region.

2. The method of claim 1, wherein said upper source region and said drain region abut a top surface of said semiconductor substrate and extend to a substantially same depth into said semiconductor substrate from said top surface.

3. The method of claim 1, wherein a bottom surface of said lower source region abuts said lower gate region, and wherein said drain region does not abut said lower gate region.

4. The method of claim 1, wherein said lower gate region laterally abuts sidewalls of said body layer and abuts said upper gate region.

5. The method of claim 1, wherein said body layer, said source region, said drain region, said upper gate region, and said lower gate region are single crystalline and epitaxially aligned among one another.

6. The method of claim 1, further comprising:

forming a first shallow trench isolation structure comprising a dielectric material, wherein an upper source region is laterally surrounded by said first shallow trench isolation structure;

forming a second shallow trench isolation structure comprising said dielectric material, wherein said drain region is laterally surrounded by said second shallow trench isolation structure; and

forming a second-conductivity-type reach-through region comprising said semiconductor material having a doping of said second conductivity type, wherein said second-conductivity-type reach-through region laterally abuts said lower gate region.

7. The method of claim 1, wherein said lower gate region is formed directly on a semiconductor layer comprising said semiconductor material, having a doping of said first conductivity type, and located in said semiconductor substrate.

8. The method of claim 1, further comprising:

forming a first-conductivity-type buried semiconductor layer comprising said semiconductor material and having a doping of said first conductivity type in said semiconductor substrate, wherein said first-conductivity-type buried semiconductor layer vertically abuts a bottom surface of said lower gate region; and

forming a semiconductor layer comprising said semiconductor material and having a doping of said second conductivity type in said semiconductor substrate, wherein said semiconductor layer vertically abuts a bottom surface of first-conductivity-type buried semiconductor layer.

9. The method of claim 1, further comprising:

forming a source-side metal semiconductor alloy region directly on said source region;

forming a drain-side metal semiconductor alloy region directly on said drain region;

forming a first gate-side metal semiconductor alloy region directly on said upper gate region; and

forming a second gate-side metal semiconductor alloy region electrically connected to said lower gate region, wherein said second gate-side metal semiconductor alloy region laterally abuts said first gate-side metal semiconductor alloy region.

10. The method of claim 9, further comprising:

forming a second-conductivity-type reach-through region comprising said semiconductor material and having a doping of said second conductivity type, wherein said second-conductivity-type reach-through region laterally abuts said lower gate region; and

forming a second-conductivity-type contact region comprising said semiconductor material and having a doping of said second conductivity type, and wherein said second-conductivity-type contact region vertically abuts said second-conductivity-type reach-through region and said second gate-side metal semiconductor alloy region.