Method of forming a semiconductor device having sub-surface trench charge compensation regions

• US 7,943,466 B2
• Filed: 01/22/2010
• Issued: 05/17/2011
• Est. Priority Date: 05/30/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Tu, Shanghui Larry, Grivna, Gordon M.
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Malek; Maliheh
• Application Number:
  US12/692,271
• Publication Number:
  US 20100140694A1
• Time in Patent Office: 480 Days
• Field of Search: 438/149, 438151-156, 438161-163, 438/167, 438/169, 438/173, 438/175, 438/197, 438/199, 438/211, 438/212, 438218-219, 438221-224, 438268-270, 438272-274, 438/282, 438/294, 438/296, 257135-136, 257/204, 257/274, 257287-288, 257/242, 257296-304, 257/328, 257/329, 257/341, 257/401, 257/901, 257E27062-E27067, 257/E27.108, 257E2163-E21644, 257E29256-E29261, 257E21394-E21458, 257E21615-E21694, 257/E27.091, 257E27095-E27096, 257/E29.131, 257/E29.118, 257/E29.198, 257/E29.2, 257/E29.274, 257/E29.313, 257/E29.318, 257/E29.262, 257/E29.201, 257/E29.655
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a semiconductor device is formed having sub-surface charge compensation regions in proximity to channel regions of the device. The charge compensation trenches comprise at least two opposite conductivity type semiconductor layers. A channel connecting region electrically couples the channel region to one of the at least two opposite conductivity type semiconductor layers.

Claims

1. A method for forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a first major surface;

forming a trench in the region of semiconductor material extending from the first major surface;

forming a plurality of semiconductor layers within the trench including at least two opposite conductivity type semiconductor layers, and at least one buffer layer separating the at least two opposite conductivity type semiconductor layers, wherein the buffer layer has a lower dopant concentration than the at least two opposite conductivity type semiconductor layers at formation;

removing portions of the plurality of semiconductor layers so that remaining portions of the plurality of semiconductor layers are recessed below the first major surface to form a sub-surface trench compensation region in a lower portion of the trench;

forming a control electrode in an upper portion of the trench overlying the sub-surface trench compensation region;

forming a body region within the region of semiconductor material, wherein the control electrode is configured to establish a channel in the body region when the device is in operation; and

forming a source region within the body region.

2. The method of claim 1, wherein the step of forming the plurality of semiconductor layers comprises the steps of:

forming a first semiconductor layer of a first conductivity type overlying sidewall and lower surfaces of the trench;

forming a first buffer layer overlying the first semiconductor layer;

forming a second semiconductor layer of a second conductivity type overlying the buffer layer;

forming a second buffer layer overlying the second semiconductor layer, wherein the first and second buffer layers have lower dopant concentrations than the first and second semiconductor layers at formation; and

forming a dielectric layer overlying the second buffer layer.

3. The method of claim 2 further comprising the steps of:

forming a cap layer on the first semiconductor layer before forming the first buffer layer;

diffusing dopants from the first semiconductor layer into the region of semiconductor material to form a second doped region of the first conductivity type; and

removing the cap layer.

4. The method of claim 1 further comprising the step of forming a channel connect region adjoining the sub-surface trench compensation region and configured to electrically couple the channel to the sub-surface trench compensation region when the device is in operation.

5. The method of claim 1 wherein the step of forming the control electrode comprises the steps of:

forming a gate dielectric layer overlying sidewalls of the trench and an upper surface of the sub-surface trench compensation region; and

forming a conductive layer overlying the gate dielectric layer.

6. The method of claim 5 further comprising the step of forming a second dielectric layer overlying the upper surface of the sub-surface trench compensation region, wherein the second dielectric layer is thicker than the gate dielectric layer.

7. A method for forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a primary surface;

forming a trench extending from the primary surface;

forming a charge compensated structure in a lower portion of the trench and spaced apart from the primary surface, wherein the charge compensated structure comprises a plurality of opposite conductivity layers overlying surfaces of the trench, and wherein the charge compensated structure is formed without an intervening dielectric layer between the region of semiconductor material and the plurality of opposite conductivity type layers;

forming a control structure in the trench and overlying the charge compensated structure, wherein the control structure includes a control electrode for forming a channel in a body region adjacent a sidewall of the trench;

forming a source region in the body region; and

forming a doped region in the region of semiconductor material to electrically couple the channel to the charge compensated structure, wherein the doped region and the source region comprise the same conductivity type, and wherein the doped region overlies at least a portion of the plurality of opposite conductivity type semiconductor layers.

8. The method of claim 7, wherein the step of forming the control structure further includes forming a first dielectric layer having a first thickness along the sidewall separating the control electrode from the region of semiconductor material, and wherein the method further includes the step of forming a second dielectric layer having a second thickness isolating the charge compensated structure from the control electrode.

9. The method of claim 8, wherein the step of forming the second dielectric layer includes forming the second dielectric so that the second thickness is greater than the first thickness.

10. The method of claim 7, wherein the step of forming the charge compensated structure includes the steps of:

forming a first layer of a first conductivity type; and

forming a second layer of a second conductivity type overlying the first layer.

11. The method of claim 10, further comprising the step of forming a dielectric layer overlying the second layer.

12. The method of claim 7, wherein the step of forming the control structure including forming the control structure where at least a portion of an upper surface of the control electrode is recessed below the primary surface of the region of semiconductor material.

13. A method of forming a semiconductor device comprising the steps of:

providing a region of semiconductor material having a first major surface;

forming a body region in the region of semiconductor material;

forming a source region in spaced relationship with the body region;

forming a sub-surface trench compensated region within the region of semiconductor material, recessed below the first major surface, and comprising a plurality of opposite conductivity type semiconductor layers, wherein one of the plurality of opposite conductivity type semiconductor layers adjoins the region of semiconductor material without an intervening dielectric layer;

forming a trench gate structure overlying the sub-surface trench compensated region including a gate conductive layer separated from sidewalls of the trench gate structure by a gate dielectric layer, wherein the body region and source region are in proximity to the trench gate structure, and wherein the trench gate structure is configured to control a channel in the body region when the semiconductor device is in operation; and

forming a channel connecting region in the region of semiconductor material so that it is interposed between the body region and the sub-surface trench compensated region and configured to electrically couple the channel to at least one of the plurality of opposite conductivity type semiconductor layers, wherein the channel connecting region and the source region comprise a first conductivity type, and wherein the channel connecting region overlies at least a portion of the plurality of opposite conductivity type semiconductor layers.

14. The method of claim 13, wherein the step of providing the region of semiconductor material includes providing a region of semiconductor material having a second conductivity type opposite to the first conductivity type, and wherein the step of forming the body region comprises forming the body region having the second conductivity type.

15. The method of claim 13, wherein the step of forming the sub-surface trench compensated region includes the steps of:

forming a trench extending from the first major surface;

forming a first single crystal epitaxial layer of a second conductivity type overlying sidewalls and a lower surface of the trench; and

forming a second single crystal epitaxial layer of the first conductivity type overlying the first layer.

16. The method of claim 15 further comprising the step of forming a dielectric region overlying the second single crystal epitaxial layer.

17. The method of claim 16, wherein the step of forming the dielectric region comprises the steps of:

forming a thermal oxide layer overlying the second layer;

forming a polysilicon layer overlying the thermal oxide layer; and

forming a deposited oxide overlying the polysilicon layer.

18. The method of claim 13 further comprising the steps of:

forming a doped region extending laterally from the sub-surface trench compensated region into the region of semiconductor material and spaced apart from the first major surface, wherein the doped region and the body region comprise a second conductivity type opposite to the first conductivity type; and

forming a second dielectric region separating a lower portion of the trench gate structure from the sub-surface trench compensated region, wherein the second dielectric region has a thickness greater than that of the gate dielectric layer.

19. The method of claim 13, wherein the step of providing the region of semiconductor material comprises providing a semiconductor substrate having a semiconductor layer formed overlying the semiconductor substrate and having a lower dopant concentration than the semiconductor substrate.

20. The method of claim 19, wherein the step of forming the sub-surface trench compensated region includes forming the sub-surface trench compensated region so that it terminates within the semiconductor layer, and wherein the method further comprises the step of forming a doped region between a lower surface of the sub-surface trench compensated region and the semiconductor substrate, wherein the doped region is configured to electrically couple the sub-surface trench compensated region to the semiconductor substrate when the device is in operation.