Semiconductor device forming method
First Claim
1. A semiconductor device, comprising:
- a substrate;
an active matrix portion formed over the substrate; and
a CPU formed over the substrate and operationally connected to the active matrix portion, each of the active matrix portion and the CPU comprising at least one thin film transistor comprising a semiconductor island including a channel region,wherein the channel region of at least one of the thin film transistors included in the active matrix portion or the CPU includes a metal selected from the group consisting of Ni, Pd, Pt, Cu, Ag, Au, In, Sn, P, As, and Sb.
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Accused Products
Abstract
In thin film transistors (TFTs) having an active layer of crystalline silicon adapted for mass production, a catalytic element is introduced into doped regions of an amorphous silicon film by ion implantation or other means. This film is crystallized at a temperature below the strain point of the glass substrate. Further, a gate insulating film and a gate electrode are formed. Impurities are introduced by a self-aligning process. Then, the laminate is annealed below the strain point of the substrate to activate the dopant impurities. On the other hand, Neckel or other element is also used as a catalytic element for promoting crystallization of an amorphous silicon film. First, this catalytic element is applied in contact with the surface of the amorphous silicon film. The film is heated at 450 to 650° C. to create crystal nuclei. The film is further heated at a higher temperature to grow the crystal grains. In this way, a crystalline silicon film having improved crystallinity is formed.
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Citations
18 Claims
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1. A semiconductor device, comprising:
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a substrate; an active matrix portion formed over the substrate; and a CPU formed over the substrate and operationally connected to the active matrix portion, each of the active matrix portion and the CPU comprising at least one thin film transistor comprising a semiconductor island including a channel region, wherein the channel region of at least one of the thin film transistors included in the active matrix portion or the CPU includes a metal selected from the group consisting of Ni, Pd, Pt, Cu, Ag, Au, In, Sn, P, As, and Sb. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device, comprising:
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a substrate; an active matrix portion formed over the substrate; and a memory formed over the substrate and operationally connected to the active matrix portion, each of the active matrix portion and the memory comprising at least one thin film transistor comprising a semiconductor island including a channel region, wherein the channel region of at least one of the thin film transistors including in the active matrix portion or the memory includes a metal selected from the group consisting of Ni, Pd, Pt, Cu, Ag, Au, In, Sn, P, As, and Sb. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor device, comprising:
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a substrate; an active matrix portion formed over the substrate; and a CPU formed over the substrate and operationally connected to the active matrix portion, each of the active matrix portion and the CPU comprising at least one thin film transistor comprising a semiconductor island including a channel region, wherein the semiconductor island in each of the thin film transistors in the active matrix portion and the CPU has a crystal growth direction approximately parallel with an upper surface of the substrate. - View Dependent Claims (12, 13, 14)
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15. A semiconductor device, comprising:
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a substrate; an active matrix portion formed over the substrate; and a memory formed over the substrate and operationally connected to the active matrix portion, each of the active matrix portion and the memory comprising at least one thin film transistor comprising a semiconductor island including a channel region, wherein the semiconductor island in each of the thin film transistors in the active matrix portion and the memory has a crystal growth direction approximately parallel with an upper surface of the substrate. - View Dependent Claims (16, 17, 18)
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Specification