Nano-tube MOSFET technology and devices

• US 7,943,989 B2
• Filed: 12/31/2008
• Issued: 05/17/2011
• Est. Priority Date: 12/31/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Inc. (Alpha & Omega Semiconductor, Ltd.)
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Ma, Wilson, Guan, Lingpeng, Bhalla, Anup, Ho, Moses, Ng, Daniel, Yilmaz, Hamza
• Primary Examiner(s): Stark; Jarrett J
• Application Number:
  US12/319,164
• Publication Number:
  US 20100163846A1
• Time in Patent Office: 867 Days
• Field of Search: 257/328, 257/329, 257/E29.257, 257/E29.262
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7322 having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

Claims

1. A semiconductor power device comprising:

a semiconductor substrate having a plurality of trenches opened from a top surface;

wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type; and

all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as one of said alternating conductivity types wherein said central gap-filler layer of a central conductivity type opposite the innermost conductivity type having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types and said central gap-filler layer constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches.

2. The semiconductor power device of claim 1 wherein:

said epitaxial layers of the alternating conductivity types in each of said trenches further include an outermost epitaxial layer covers directly on sidewalls of said trenches wherein said outmost epitaxial layer having an opposite conductivity type from said pillar conductivity type; and

wherein the nano tubes, the central gap-filler layer, and the pillars are substantially charge balanced.

3. The semiconductor power device of claim 1 wherein:

said central gap-filler layer comprises a lightly doped silicon with a dopant concentration equal to or less than 10% of a dopant concentration of said two innermost epitaxial layers constituting two adjacent nano tubes surrounding said central gap-filler layer.

5. The semiconductor power device of claim 1 wherein:

said pillars between two adjacent trenches with sidewalls covering by said epitaxial layers of the alternating conductivity types have a width approximately half to one-fourth of a width of said trenches and significantly greater than the width of said epitaxial layer of said alternating conductivity and said central gap-filler layer.

6. The semiconductor power device of claim 1 wherein:

said plurality of trenches each having a width of about ten microns and said plurality of trenches are separated by a said pillar from adjacent trenches wherein said pillar having a width ranging substantially between two to five microns.

7. The semiconductor power device of claim 1 wherein:

said plurality of trenches each having a width of about ten microns with the sidewalls covered by the epitaxial layers of alternating conductivity types constituting said nano tubes having a layer thickness ranging substantially between about 0.2 to 2 microns and wherein said central gap-filler layer having a layer thickness substantially in a same range as said epitaxial layers of alternating conductivity types.

8. The semiconductor power device of claim 1 wherein:

said plurality of trenches each having a trench depth ranging substantially between 5 to 120 micrometers.

9. The semiconductor power device of claim 1 wherein:

said semiconductor substrate further comprising a nano tube merger region comprises a doped layer is disposed below said trenches having sidewalls covered by said nano tubes and below said pillars between said trenches and extended laterally across the semiconductor substrate.

10. The semiconductor power device of claim 1 wherein:

the sidewalls of said plurality of trenches having a slightly tilted angle relative to a vertical perpendicular direction relative to a bottom surface of said semiconductor substrate.

11. The semiconductor power device of claim 1 wherein:

said semiconductor substrate comprising a bottom substrate layer of a first conductivity type and said pillars having a second conductivity type.

12. The semiconductor power device of claim 1 wherein:

said semiconductor substrate comprising a bottom substrate layer of a first conductivity type and said pillars having a same conductivity type with the conductivity type of said bottom substrate layer.

13. The semiconductor power device of claim 1 wherein:

the pillars constitute the semiconductor volumes comprising a lightly doped epitaxial layer.

14. The semiconductor power device of claim 1 wherein:

the pillars constitute the semiconductor volumes comprising volumes of a single crystal semiconductor substrate.

4. A semiconductor power device comprising:

a semiconductor substrate having a plurality of trenches opened from a top surface of said semiconductor substrate;

wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type; and

all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as one of said alternating conductivity types wherein said central gap-filler layer is a dielectric layer having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches.

15. A semiconductor power device comprising:

a semiconductor substrate having a plurality of trenches opened from a top surface having slightly tilt sidewalls having a smaller trench bottom area than a top trench opening area;

wherein every two adjacent trenches are separated by a volume of said semiconductor substrate constituting a pillar having a pillar conductivity type; and

all sidewalls of each of said trenches are covered by a plurality of epitaxial layers of alternating conductivity types disposed on two opposite sides and substantially symmetrical to a central gap-filler layer disposed between two innermost epitaxial layers of an innermost conductivity type as one of said alternating conductivity types wherein said central gap-filler layer of a central conductivity type opposite the innermost conductivity type having a width substantially the same as said plurality of epitaxial layers of alternating conductivity types and significantly smaller than said pillar, and wherein said epitaxial layers of said alternating conductivity types and said central gap-filler layer constituting nano tubes functioning as conducting channels extending along a sidewall direction of each of said trenches.

16. The semiconductor power device of claim 15 wherein:

a total even number of said epitaxial layers of said alternating conductivity types are disposed on said two opposite sides of said central gap-filler layer.

17. The semiconductor power device of claim 16 wherein:

said epitaxial layers of the alternating conductivity types in each of said trenches further include an outermost epitaxial layer covers directly on sidewalls of said trenches wherein said outmost epitaxial layer having an opposite conductivity type from said pillar conductivity type; and

wherein the nano tubes, the central gap-filler layer, and the pillars are substantially charge balanced.

18. The semiconductor power device of claim 16 wherein:

said central gap-filler layer comprises a lightly doped silicon with a dopant concentration equal to or less than 10% of a dopant concentration of said two innermost epitaxial layers constituting two adjacent nano tubes surrounding said central gap-filler layer.