Power semiconductor device with interconnected gate trenches

• US 7,943,990 B2
• Filed: 08/14/2006
• Issued: 05/17/2011
• Est. Priority Date: 08/17/2005
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling, Amali, Adam I., Turner, Russell
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US11/504,751
• Publication Number:
  US 20070040215A1
• Time in Patent Office: 1,737 Days
• Field of Search: 257213-413, 257/E29.257
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device which includes a plurality of gate trenches and a perimeter trench intersecting the gate trenches.

Claims

1. A power semiconductor device comprising:

a drift region of a first conductivity;

a base region of a second conductivity over said drift region;

a plurality of first gate trenches extending through said base region to said drift region;

conductive regions of said first conductivity adjacent said first gate trenches;

a first power electrode electrically coupled to said conductive regions of said first conductivity;

a first perimeter trench disposed around and intersecting said first gate trenches, said first perimeter trench including a first section and a second section, said first section intersecting said first gate trenches and said second section extending along a same direction as said first gate trenches;

a gate insulation layer formed in each first gate trench adjacent said base region;

a gate electrode residing in each first gate trench and said first perimeter trench; and

a gate bus disposed at least over a portion of said perimeter trench and electrically connected to said gate electrode in said perimeter trench, said gate bus surrounding at least a portion of said power electrode by including first and second integrally formed portions, said first portion extending along said first section and a second portion extending along said same direction as said first gate trenches, wherein said power electrode includes one edge opposite and spaced from said first portion of said gate bus and another edge opposite and spaced from said second portion of said gate bus.

2. The power semiconductor device of claim 1, wherein said perimeter trench is a termination trench.

3. The power semiconductor device of claim 1, further comprising a termination trench disposed around said perimeter trench.

4. The power semiconductor device of claim 3, further comprising an EQR trench around said termination trench.

5. The power semiconductor device of claim 1, wherein said gate electrode is comprised of conductive polysilicon.

6. The power semiconductor device of claim 1, wherein said gate insulation layer is comprised of silicon dioxide.

7. The power semiconductor device of claim 1, wherein each said gate trench includes a curved bottom portion.

8. The power semiconductor device of claim 1, further comprising an insulation body disposed at the bottom of each first gate trench, said insulation body being thicker than said gate insulation layer.

9. The power semiconductor device of claim 1, wherein said drift region is disposed over a substrate.

10. The power semiconductor device of claim 9, wherein said substrate is comprised of silicon.

11. The power semiconductor device of claim 1, wherein said power semiconductor device is a MOSFET.

12. The power semiconductor device of claim 1, wherein said power semiconductor device is an IGBT.

13. The power semiconductor device of claim 1, further comprising a plurality of second gate trenches extending through said base region into said drift region;

a second perimeter trench disposed around and intersecting said second gate trenches;

a second gate insulation layer formed in each second gate trench adjacent said base region; and

a second gate electrode residing in each second gate trench.

14. The power semiconductor device of claim 1, wherein said gate bus extends into and forms a field plate in a termination region of said device.

15. The power semiconductor device of claim 1, wherein said termination region includes a termination trench and said gate bus extends into and forms a field plate inside said termination trench.

16. The power semiconductor device of claim 15, comprising a field insulation body overlying the bottom surface and the sidewalls of said termination trench, said field insulation body having a thickness greater than that of said gate insulation layer.

17. The power semiconductor device of claim 15, comprising a field insulation body overlying the bottom surface and the sidewalls of said termination trench, said field insulation body comprising a first silicon dioxide body and a second silicon dioxide body overlying said first silicon oxide body.

18. The power semiconductor device of claim 17, wherein said second silicon dioxide body extends out of said termination trench underneath said gate bus.

19. The power semiconductor device of claim 1, wherein said gate bus completely surrounds said power electrode.